UPD16680P NEC [NEC], UPD16680P Datasheet - Page 7
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UPD16680P
Manufacturer Part Number
UPD16680P
Description
1/53, 1/40 DUTY, LCD CONTROLLER/DRIVER WITH BUILT-IN RAM
Manufacturer
NEC [NEC]
Datasheet
1.UPD16680P.pdf
(44 pages)
3.2 Logic System Pins (1/2)
WS
DA
STB
E(SCK)
D
D
D
D
TEST
/RESET
0
1
4
7
Pin Symbol
(DATA)
(NS)
CHA
to D
to D
OUT
3
6
Word length select pin
(Word Select)
D/A converter select pin
Strobe
Enable(shift clock)
Data-bus(data)
Data-bus
Data-bus
Data-bus(nibble select)
TEST signal output
Reset
Pin Name
85 to 87
88 to 90
Pin No.
92
78
93
94
84
91
97
95
Data Sheet S12694EJ2V0DS00
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
This pin selects the word length.
At High level, it become an 8-bit parallel interface.
At Low level, when D
When the word length is 4 bits, data is transferred in the
upper-to-low sequence by mean of data busses D
The word length cannot be changed after power-on.
LCD driving voltage adjustment or not.
At High level, D/A converter is used. At Low level, unused.
This pin is select signal of device, strobe signal for data
transfer. Data transfer is initialized at falling/rising edge of
STB.
Data can be input/output at Low level either in parallel
interface or serial interface mode.
When STB is High level, Enable/shift clock is bypassed.
When using parallel interface mode, this pin becomes the
data enable input. In reading-in, data is fetched into the
interface buffer at rising edge. In reading-out, data is fetched
from interface buffer at falling edge.
When using serial interface mode, this pin becomes the data
shit clock.
In reading-in, data is fetched into the interface buffer at rising
edge.
In reading-out, data is fetched from interface buffer at falling
edge.
bit of data-bus.
When using serial interface mode, this pin becomes the
input/output pin of the command and display data (3 states).
When using parallel interface mode, these pin becomes the
D
keep them H or L.
When using parallel interface mode, these pin become the D
to D
them H or L.
When word select (WS) is High level, this pin becomes the D
bit of data-bus.
When word select (WS) is Low level, This pin becomes nibble
select pin. At High level, selected 4-bit parallel interface.
At Low level, selected serial interface.
When to do test, this pin is output for test signal.
When using in normal operation, this pin leave open.
At Low level, the PD16680 is initialized.
This pin selects whether to use the internal D/A converter for
When using parallel interface mode, this pin becomes the D
interface.
1
to D
6
bits of data-bus. When using serial interface mode, keep
3
bits of data-bus. When using serial interface mode,
Function Description
7
(NS) is High level, it become a serial
0
to D
PD16680
3
.
0
4
7
7