kac-9637 ETC-unknow, kac-9637 Datasheet - Page 31

• Manufacturer Part Number: kac-9637
• Description: Cmos Image Sensor 648 H X 488 V Vga 68 Fps Monochrome Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Register Set
Register Name VSYNC Latency Register
Address
Mnemonic
Type
Reset Value
Register Name HSYNC Latency Register
Address
Mnemonic
Type
Reset Value
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7:6
4:0
7:4
3:0
Bit
Bit
VsyncEnd
HsyncEnd
Bit Symbol
Bit Symbol
50 Hex
VSYCADJUST
Read/Write
08 Hex.
51 Hex
HSYNCADJUST
Read/Write
08 Hex.
(continued)
Reserved.
By default, in pulse mode the
vsync signal will remain active
for four pclk periods after end of
frame. In level mode vsync will
remain active for the duration of
the frame delay time.
Use to adjust the time that the
vsync signal goes inactive in
multiples of pclk as follows:
Reserved.
By default, in pulse mode the
hsync signal will remain active
for four pclk periods after end of
each row. In level mode hsync
will remain active for the dura-
tion of the row delay time.
Use to adjust the time that the
hsync signal goes inactive in
multiples of pclk as follows:
0000
00001
to
00111
01000
01001
to
11111
0000
0001
to
0111
01000
1001
to
1111
Description
Description
no vsync pulse
Reserved
no adjustment, the
default
+1 pclk clock
to
+24 pclk clocks
no hsync pulse
Reserved
no adjustment, the
default
+1 pclk clock
to
+8 pclk clocks
31
Register Name Synchronization Adjustment Register
Address
Mnemonic
Type
Reset Value
7:4
3:0
Bit
VsyncStart
HsyncStart
Bit Symbol
52 Hex
DVBUSCONFIG0
Read/Write
00 Hex.
By default, in pulse mode the
vsync signal will remain active
for four pclk periods after end of
frame. In level mode vsync will
remain active for the duration of
the frame delay time.
Use to adjust the time that the
vsync signal goes active in mul-
tiples of pclk as follows:
By default, in pulse mode the
hsync signal will remain active
for four pclk periods after end of
row. In level mode hsync will
remain active for the duration of
the row delay time.
Use to adjust the time that the
hsync signal goes active in mul-
tiples of pclk as follows:
0000
to
1111
0000
to
1111
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Description
0 pclk clocks
to
-15 pclk clock
0 pclk clocks
to
-15 pclk clock