kac-9637 ETC-unknow, kac-9637 Datasheet - Page 32

• Manufacturer Part Number: kac-9637
• Description: Cmos Image Sensor 648 H X 488 V Vga 68 Fps Monochrome Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Register Set
Register Name Polarity Adjustment Register
Address
Mnemonic
Type
Reset Value
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7
6
5
4
3:2
1
0
Bit
PixClkMode
VsyncMode
HsyncMode
VsyncPol
HsyncPol
Bit Symbol
53 Hex
DVBUSCONFIG1
Read/Write
0C Hex.
(continued)
Reserved
Set the to a logic 1 to operate
pclk to “data ready mode”. Set
to a logic 0, the default, to set
pclk to “free running mode”.
Set to a logic 1 to operate the
vsync pin to “pulse mode”. Set
to a logic 0, (the default) to oper-
ate the vsync signal to “level
mode”.
Set to a logic 1 to operate the
hsync signal to pulse for a mini-
mum of four pixel clocks at the
end of each row. Set to a logic
0, (the default) to force the
hsync signal to a level indicat-
ing valid data within a row.
Reserved
Assert to force the vsync signal
to generate a logic 1 during a
frame readout (Level Mode), or
a negative pulse at the end of a
frame readout (Pulse Mode).
Clear (the default) to force the
vsync signal to generate a logic
0 during a frame readout (Level
Mode), or a positive pulse at the
end of a frame readout (Pulse
Mode).
NOTE: In slave mode this bit
must be set to 0.
Assert to force the hsync signal
to generate a logic 1 during a
row readout (Level Mode), or a
negative pulse at the end of a
row readout (Pulse Mode).
Clear (the default) to force the
hsync signal to generate a logic
0 during a row readout (Level
Mode), or a positive pulse at the
end of a readout (Pulse Mode).
NOTE: In slave mode this bit
must be set to 0.
Description
32
Register Name Video Output Adjustment Register
Address
Mnemonic
Type
Reset Value
7
6
5
4
3:0
Bit
OutputEn
BlkPixelEn
PixClkPol
Bshift[3:0]
Bit Symbol
54 Hex
DVBUSCONFIG2
Read/Write
F0 Hex.
Set to a logic 0 to tri-state all
output signals (data and control)
on the digital video port. set to a
logic 1, (the default) to enable
all signals (data and control) on
the digital video port.
Set to a logic 1, (the default) to
read out the middle 8 black pix-
els at the start of every row. Set
to a logic 0 to mask out the
black pixel readout.
NOTE: In master mode when
the black pixels are enabled the
active edge of Hsync corre-
sponds to the first black pixel.
Set to a logic 1 to set the active
edge of the pixel clock to nega-
tive. Set to a logic 1, (the
default), to set the active edge
of the clock to positive.
Reserved
Use to program the routing of
the MSB output of the internal
video A/D to a bit on the digital
video bus.
0000 A/D[9:0] -> d[9:0]
0001 A/D[9:0] -> d[8:0],d[9]
0010 A/D [9:0] ->d[7:0],d[9:8]
0011 A/D [9:0] -> d[6:0],d[9:7]
0100 A/D [9:0] -> d[5:0],d[9:6]
0101 A/D[9:0] -> d[4:0],d[9:5]
0110 A/D [9:0] -> d[3:0],d[9:4]
0111 A/D [9:0] -> d[2:0],d[9:3]
1000 A/D [9:0] ->d[1:0],d[9:2]
1001 A/D [9:0] -> d[0],d[9:1]
1010 A/D [9:0] -> d[9:0]
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Description