UPD43256B-A NEC [NEC], UPD43256B-A Datasheet - Page 13

• Manufacturer Part Number: UPD43256B-A
• Description: 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT
• Manufacturer: NEC [NEC]

Write Cycle Timing Chart 1 (WE Controlled)
Cautions 1. CS or WE should be fixed to high level during address transition.
Remarks 1. Write operation is done during the overlap time of a low level CS and a low level WE.
I/O (Input/Output)
Address (Input)
WE (Input)
CS (Input)
2. When WE is at low level, the I/O pins are always high impedance. When WE is at high level,
3. If CS changes to low level at the same time or after the change of WE to low level, the I/O pins
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite
in phase with output signals.
read operation is executed. Therefore OE should be at high level to make the I/O pins high
impedance.
will remain high impedance state.
Indefinite data out
t
AS
t
WHZ
t
AW
t
CW
t
WC
High
impe-
dance
t
WP
t
DW
Data in
t
t
DH
WR
t
OW
High
impe-
dance
Indefinite data out
PD43256B
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