edd51163dbh-ls Elpida Memory, Inc., edd51163dbh-ls Datasheet - Page 23

• Manufacturer Part Number: edd51163dbh-ls
• Description: 512m Bits Ddr Mobile Ram
• Manufacturer: Elpida Memory, Inc.

Extended Mode Register
The extended mode register is as follows;
Reserved
Driver Strength
Partial Array Self-Refresh
Following extended mode register programming, no command can be issued before at least 2 clocks have elapsed.
Driver Strength
By setting specific parameter on A6 and A5, driving capability of data output drivers is selected.
Auto Temperature Compensated Self-Refresh (ATCSR)
The DDR Mobile RAM automatically changes the self-refresh cycle by on die temperature sensor. No extended
mode register program is required. Manual TCSR (Temperature Compensated Self-Refresh) is not implemented.
Partial Array Self-Refresh
Memory array size to be refreshed during self-refresh operation is programmable in order to reduce power. Data
outside the defined area will not be retained during self-refresh.
Deep Power-Down Exit Sequence
In order to exit from the deep power-down mode and enter into the idle mode, the following sequence is needed,
which is similar to the power-on sequence.
(1) A 200 s or longer pause must precede any command other than ignore command (DESL).
(2) After the pause, all banks must be precharged using the precharge command (the precharge all banks command
(3) Once the precharge is completed and the minimum tRP is satisfied, two or more Auto-refresh must be performed.
(4) Both the mode register and the extended mode register must be programmed. After the mode register set cycle
Remarks:
1 The sequence of Auto-refresh, mode register programming and extended mode register programming above may
2 CKE must be held high.
Preliminary Data Sheet E1433E21 (Ver. 2.1)
is convenient).
or the extended mode register set cycle, tMRD (2 clocks minimum) pause must be satisfied.
be transposed.
BA1
1
BA0
0
A6
0
0
1
1
A12
0
A5
0
1
0
1
A11 A10
Driver Strength
Normal
1/2 strength
1/4 strength
1/8 strength
0
0
Extended Mode Register Set
: A12 through A7, A4, A3
: A6 through A5
: A2 through A0
A9
0
A8
0
23
A7
0
A2
A6
0
0
0
0
1
1
1
1
DS
A1
0
0
1
1
0
0
1
1
A5
A0
0
1
0
1
0
1
0
1
A4
0
Bank0 & Bank1 (BA1 = 0)
Bank0 (BA = BA1 = 0)
A3
0
Refresh Array
Reserved
Reserved
Reserved
Reserved
Reserved
All banks
A2
EDD51163DBH-LS
PASR
A1
A0