edd51163dbh-ls Elpida Memory, Inc., edd51163dbh-ls Datasheet - Page 9

• Manufacturer Part Number: edd51163dbh-ls
• Description: 512m Bits Ddr Mobile Ram
• Manufacturer: Elpida Memory, Inc.

Parameter
Autoprecharge write recovery and
precharge time
Self-refresh exit period
Internal Write to Read command delay
Average periodic refresh interval
Notes: 1. On all AC measurements, we assume the test conditions shown in “Test conditions” and full driver
Test Conditions
Parameter
Input high voltage
Input low voltage
Input differential voltage, CK and /CK inputs
Input differential cross point voltage,
CK and /CK inputs
Input signal slew rate
Output load
Preliminary Data Sheet E1433E21 (Ver. 2.1)
DQOUT
/CK
CK
(DQOUT)
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
3. The timing reference level is VDDQ/2.
4. Output valid window is defined to be the period between two successive transition of data out signals.
5. tHZ is defined as DOUT transition delay from low-Z to high-Z at the end of read burst operation. The
6. tLZ is defined as DOUT transition delay from high-Z to low-Z at the beginning of read operation. This
7. The transition from low-Z to high-Z is defined to occur when the device output stops driving. A specific
8. tAC, tDQSCK, tHZ and tLZ are specified with 15pF bus loading conditio
strength is assumed for the output load, that is both A6 and A5 of EMRS is set to be “L”.
transition is defined to occur when the signal level crossing VDDQ/2.
The signal transition is defined to occur when the signal level crossing VDDQ/2.
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
reference voltage to judge this transition is not given.
tLZ
tCH
tCK
Q1
tAC
Test Condition (Wave form and Timing Reference)
tCL
Symbol
tDAL
tSREX
tWTR
tREF
Q2
VID
Symbol
VIH (AC)
VIL (AC)
VID (AC)
VIX (AC)
SLEW
CL
VDDQ/2
VIX
-5BLS
min.
tWR + tRP
120
2
—
DQ
Output Load
9
max.
—
—
—
7.8
1
Value
1.6
0.2
1.4
VDDQ/2 with VDD=VDDQ
15
CL
T
-6ELS
min.
tWR + tRP
120
1
—
slew rate =
n.
(V
EDD51163DBH-LS
IH
max.
—
—
—
7.8
T
V
IL
Unit
V
V
V
V
V/ns
pF
)
Unit
tCK
ns
ns
µs
VIH (=1.6V)
VIL (=0.2V)
Note
Notes