DS2430A+R DALLAS [Dallas Semiconductor], DS2430A+R Datasheet - Page 12

• Manufacturer Part Number: DS2430A+R
• Description: 256-Bit 1-Wire EEPROM
• Manufacturer: DALLAS [Dallas Semiconductor]

DS2430A
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Application Note
187 for a comprehensive discussion of a search ROM, including an actual example.
1-Wire Signaling
The DS2430A requires strict protocols to insure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read
Data. All these signals (except Presence Pulse) are initiated by the bus master. The initialization sequence
required to begin any communication with the DS2430A is shown in Figure 9. A Reset Pulse followed by
a Presence Pulse indicates the DS2430A is ready to accept a ROM command. The bus master transmits
(TX) a Reset Pulse (t
, minimum 480µs). The bus master then releases the line and goes into receive
RSTL
mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After detecting the rising edge
on the data pin, the DS2430A waits (t
, 15µs to 60µs) and then transmits the Presence Pulse (t
, 60µs
PDH
PDL
to 240µs).
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 9
In order not to mask interrupt signaling by other devices on the 1-Wire bus, t
+ t
should always be
RSTL
R
less than 960µs.
Read/Write Time Slots
The definitions of write and read time slots are illustrated in Figure 10. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS2430A to the
master by triggering a delay circuit in the DS2430A. During write time slots, the delay circuit determines
when the DS2430A will sample the data line. For a read data time slot, if a “0” is to be transmitted, the
delay circuit determines how long the DS2430A will hold the data line low overriding the 1 generated by
the master. If the data bit is a “1”, the DS2430A will leave the read data time slot unchanged.
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