DS26303L-XXX DALLAS [Dallas Semiconductor], DS26303L-XXX Datasheet - Page 48

• Manufacturer Part Number: DS26303L-XXX
• Description: 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
• Manufacturer: DALLAS [Dallas Semiconductor]

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: QRSS Enable (QRSS). When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and
PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a
generating polynomial of x
are all 0.
Bit 5: Pattern Type Select (PTS). When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]). These bits control the “length” feedback of the pattern
generator. The length feedback is from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal, the
feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 4 to 0: Pattern Tap Feedback (PTF[4:0]). These bits control the PRBS “tap” feedback of the pattern
generator. The tap feedback is from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored when
programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y.
—
—
7
0
7
0
QRSS
20
—
+ x
6
0
6
0
17
BPCR1
BERT Pattern Configuration Register 1
02h
BPCR2
BERT Pattern Configuration Register 2
03h
+ 1. The output of the pattern generator is forced to one if the next 14 output bits
PTS
—
5
0
5
0
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
48 of 101
PLF4
PTF4
4
0
4
0
PLF3
PTF3
3
0
3
0
PLF2
PTF2
2
0
2
0
PTF1
PLF1
1
0
1
0
PTF0
PLF0
0
0
0
0