DS1877T+TR MAXIM [Maxim Integrated Products], DS1877T+TR Datasheet - Page 46
DS1877T+TR
Manufacturer Part Number
DS1877T+TR
Description
SFP Controller for Dual Rx Interface
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet
1.DS1877TTR.pdf
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Table 02h, Register 89h: CNFGB
SFP Controller for Dual Rx Interface
46
89h
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
A2h AND B2h MEMORY
MEMORY TYPE
INXC
BIT 7
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
INXC: INX software control bit (see Figure 11).
0 = INX pin’s logic controls OUTX pin.
1 = OUTX is active (bit 6 defines the polarity).
INVOUTX: Inverts the active state for OUTX (see Figure 11).
0 = Noninverted.
1 = Inverted.
ALATCH2: ADC alarm’s comparison latch, Lower Memory, Registers 70h–71h.
0 = ADC alarm and flags reflect the status of the last comparison.
1 = ADC alarm flags remain set.
QTLATCH2: QT’s comparison latch, Lower Memory, Register 73h.
0 = QT alarm and warning flags reflect the status of the last comparison.
1 = QT alarm and warning flags remain set.
WLATCH2: ADC warning’s comparison latch, Lower Memory, Register 74h.
0 = ADC warning flags reflect the status of the last comparison.
1 = ADC warning flags remain set.
ALATCH1: ADC alarm’s comparison latch, Lower Memory, Registers 70h–71h.
0 = ADC alarm and flags reflect the status of the last comparison.
1 = ADC alarm flags remain set.
QTLATCH1: QT’s comparison latch, Lower Memory, Register 73h.
0 = QT alarm and warning flags reflect the status of the last comparison.
1 = QT alarm and warning flags remain set.
WLATCH1: ADC warning’s comparison latch, Lower Memory, Register 74h.
0 = ADC warning flags reflect the status of the last comparison.
1 = ADC warning flags remain set.
INVOUTX
00h
PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
PW2 or (PW1 and RWTBL2)
Common A2h and B2h memory locations
Nonvolatile (SEE)
ALATCH2
QTLATCH2
WLATCH2
ALATCH1
QTLATCH1
WLATCH1
BIT 0
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