cl-cr3430 Cirrus Logic, Inc., cl-cr3430 Datasheet - Page 2

• Manufacturer Part Number: cl-cr3430
• Manufacturer: Cirrus Logic, Inc.

FEATURES
OVERVIEW
The built-in ADB (audio data buffering) interface elimi-
nates slowing the motor down from 45 to 1 for digital
audio data. This feature is especially useful in CAV
(constant angular velocity) designs where motor
speed remains constant regardless of the data type,
either audio or data, read from the disc.
The CL-CR3430 includes support for CD-TEXT mode,
a new subcode format. In this mode, the subcode R-W
data is stored in the buffer without de-interleaving and
de-scrambling, allowing storage of short messages
such as song titles.
The CL-CR3430 supports realtime layered ECC cor-
rection, which is programmable for up to 64 P/Q-word
corrections per sector. Also, subcode R-W correction
is supported in the CD-DA (CD-Digital Audio) mode.
The CL-CR3430 DSP interface supports many
CD-ROM DSPs from various manufacturers. It
includes three types of interface signals: the main
— Sector header validity check is done in hardware during
— Realtime CD-ROM layered ECC correction with up to 64
— Supports realtime subcode error correction in CD-DA
— Supports Philips subcode interface
Audio DAC Interface
— Supports ADB for CD-DA audio play mode
— Supports buffer streaming during the Disc-to-DAC data
— Supports various DACs
ATAPI Host Interface
— Supports Synchronous Ultra DMA/33 data transfer pro-
— Supports ATA PIO Modes 3 and 4 transfers without
— FIFOs synchronize buffer RAM access with the host bus
— Hardware implementation of:
— Supports any host speed with programmable and auto
data transfer
programmable sets of P/Q-word corrections per sector
(CD-Digital Audio) mode
transfer
tocol with data rate up to 33.3 Mbytes/sec.
IOCHRDY and supports DMA Modes 1 and 2
and the DSP data transfer
wait-state generation
ATAPI packet command
ATAPI reset command
(cont.)
(cont.)
data channel signals, subcode channel signals, and
serial DSP programming signals.
The ATAPI host interface is designed for compliance
with ATAPI Specification SFF-8020, Revision 1.2. The
ATAPI Command and Control Block registers are con-
tained in the CL-CR3430 register set, allowing both
host and local microcontroller accesses. The
CL-CR3430 supports some ATAPI protocols in hard-
ware without microcontroller intervention (such as
ATAPI packet and ATAPI reset commands).
The buffer manager controls the flow of data between
the host and DSP interfaces. These interfaces store
and retrieve data to/from the external buffer memory
using interleaved access cycles. The actual buffer
memory is implemented with DRAMs. The buffer man-
ager can be programmed to provide all the necessary
address and control signals for RAM devices with
varying access times and memory configurations.
— True realtime hardware/software ATAPI compatibility
— All ATAPI command and control registers contained in
— Direct interface to ATAPI bus with programmable 4- or
— Can daisy-chain two ATA- or ATAPI-embedded drives
Buffer Manager
— Supports 8- and 16-bit DRAM
— Dual-port circular buffer control with access-priority
— Supports streaming operation
— Direct addressing of up to 4 Mbytes of DRAM
— Supports variable buffer segmentation
— Programmable timing control for DRAM
— Host overrun control
Microcontroller Interface
— Supports high-speed Intel - and Motorola -type
— Supports nonmultiplexed and multiplexed address and
— Interrupt- or polled-microcontroller interface
— Three-level power-down capability when idle and auto-
the CL-CR3430 register set
12-mA drivers
resolver
microcontrollers
data buses
matic power-up when command is received
ATAPI CD-ROM Decoder
CL-CR3430