ex256-ptq64pp Actel Corporation, ex256-ptq64pp Datasheet - Page 9

• Manufacturer Part Number: ex256-ptq64pp
• Description: Ex Family Fpgas
• Manufacturer: Actel Corporation

Other Architectural Features
Performance
The combination of architectural features described
above enables eX devices to operate with internal clock
frequencies exceeding 350 MHz for very fast execution
of complex logic functions. The eX family is an optimal
platform upon which the functionality previously
contained in CPLDs can be integrated. eX devices meet
the performance goals of gate arrays, and at the same
time, present significant improvements in cost and time
to market. Using timing-driven place-and-route tools,
designers can achieve highly deterministic device
performance.
User Security
The Actel FuseLock advantage ensures that unauthorized
users will not be able to read back the contents of an
Actel antifuse FPGA. In addition to the inherent
strengths of the architecture, special security fuses that
prevent internal probing and overwriting are hidden
throughout the fabric of the device. They are located
such that they cannot be accessed or bypassed without
destroying the rest of the device, making both invasive
and more-subtle noninvasive attacks ineffective against
Actel antifuse FPGAs.
Look for this symbol to ensure your valuable IP is secure.
Figure 1-7 • Fuselock
For more information, refer to
Security in Actel Antifuse FPGAs
I/O Modules
Each I/O on an eX device can be configured as an input,
an output, a tristate output, or a bidirectional pin. Even
without the inclusion of dedicated I/O registers, these I/
Os, in combination with array registers, can achieve
clock-to-out (pad-to-pad) timing as fast as 3.9 ns. I/O cells
in eX devices do not contain embedded latches or flip-
flops and can be inferred directly from HDL code. The
device can easily interface with any other device in the
system, which in turn enables parallel design of system
components and reduces overall design time.
FuseLock
Actel's Implementation of
application note.
v4.3
All unused I/Os are configured as tristate outputs by
Actel's Designer software, for maximum flexibility when
designing new boards or migrating existing designs. Each
I/O module has an available pull-up or pull-down resistor
of approximately 50 kΩ that can configure the I/O in a
known state during power-up. Just shortly before V
reaches 2.5 V, the resistors are disabled and the I/Os will be
controlled by user logic.
Table 1-2
more information on I/Os, refer to
RT54SX-S I/Os
Table 1-2 • I/O Features
The eX family supports mixed-voltage operation and is
designed to tolerate 5.0 V inputs in each case.
A detailed description of the I/O pins in eX devices can be
found in
Function
Input
Threshold
Selection
Nominal
Output Drive
Output Buffer “Hot-Swap” Capability
Power-Up
Buffer
"Pin Description" on page
describes the I/O features of eX devices. For
application note.
Description
•
•
•
•
•
•
•
•
Selectable on an individual I/O basis
Individually selectable low-slew option
Individually selectable pull ups and pull downs
during power-up (default is to power up in
tristate)
Enables deterministic power-up of device
V
CCA
5.0V TTL
3.3V LVTTL
2.5V LVCMOS2
5.0V TTL/CMOS
3.3V LVTTL
2.5V LVCMOS 2
I/O on an unpowered device does not sink
current
Can be used for “cold sparing”
and V
CCI
can be powered in any order
1-26.
Actel eX, SX-A, and
eX Family FPGAs
CCA
1-5