UPD77210F1-DA2 NEC [NEC], UPD77210F1-DA2 Datasheet
UPD77210F1-DA2
Related parts for UPD77210F1-DA2
UPD77210F1-DA2 Summary of contents
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FIXED-POINT DIGITAL SIGNAL PROCESSOR The µ PD77210 and 77213 are 16-bit fixed-point digital signal processors (DSP). Compared with the existing members of the µ PD77111 Family, the µ PD77210 Family consumes less power and is ideal for battery-driven mobile ...
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Supply voltage -DSP core supply voltage: 1.425 to 1.65 V (MAX. operating speed 120 MHz), 1.55 to 1.65 V (MAX. operating speed 160 MHz) µ PD77210 only -I/O pin supply voltage: 2.7 to 3.6 V ORDERING INFORMATION Parts Number ...
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Peripheral unit External External memory memory I/O Note SD Card I/O Serial I/O (AUDIO) Serial I/O (TDM) Host I/O DMA controller Interrupt controller Port Timer IE I/O RESET X bus Y bus X memory Y memory X memory Y memory ...
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FUNCTIONAL PIN BLOCK Serial interface (time division serial) Serial interface (audio serial) Note SD card interface Port 16 2 Host interface 16 Note µ PD77213 only Caution Some port pins, host interface pins, serial interface pins, interrupt pins, and SD ...
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DSP FUNCTION LIST µ PD77110 µ PD77111 Item 35.5 K × 32 Memory Int. instruction RAM space Int. instruction ROM None (words × × 16 each Data RAM bits) (X/Y memory) Data ROM None (X/Y memory) Ext. instruction ...
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PIN CONFIGURATIONS 161-pin plastic fine pitch BGA (10 x 10) • µ µ µ µ PD77210F1-DA2 • µ µ µ µ PD77213F1-xxx-DA2 (Bottom View ...
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Pin No. Pin Name Pin No C14 P10/HD10/INT22 A3 P5/INT11 D2 P11/HD11/INT32 A4 P2/INT20 D3 P12/HD12/INT03 A5 GND D4 GND GND P1/INT10 GND ...
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LQFP (fine pitch) (20 x 20) (Top View) • µ µ µ µ PD77210GJ-8EN • µ µ µ µ PD77213GJ-xxx-8EN 144 143 142 141 140 139 138 137 136 135 134 1 GND TCK 2 TDI 3 TMS ...
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Pin No. Pin Name Pin No. 1 GND 37 2 TCK 38 3 TDI 39 4 TMS 40 5 TRST GND 45 10 RESET 46 11 STOPS 47 ...
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Pin Name ASCK :Audio Serial Clock Input/Output ASI :Audio Serial Data Input ASIEN :Audio Serial Input Enable ASO :Audio Serial Data Output ASOEN :Audio Serial Output Enable BCLK :Bit Clock Input/Output CLKIN :Clock Input CLKOUT :Clock Output CSTOP :Clear Stop ...
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PIN FUNCTIONS....................................................................................................................................13 1.1 Description of Pin Functions ........................................................................................................................13 1.2 Connection of Unused Pins ..........................................................................................................................21 1.2.1 Connection of functional pins ..................................................................................................................21 1.2.2 Connection of non-functional pin .............................................................................................................22 2. FUNCTIONAL OUTLINE .......................................................................................................................23 2.1 Program Control Unit.....................................................................................................................................23 2.1.1 CPU control .............................................................................................................................................23 2.1.2 ...
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Host reboot ............................................................................................................................................. 30 5.2.3 Serial reboot ........................................................................................................................................... 30 6. STANDBY MODE.................................................................................................................................. 31 6.1 Halt Mode ....................................................................................................................................................... 31 6.2 Stop Mode ...................................................................................................................................................... 31 7. MEMORY MAP...................................................................................................................................... 32 7.1 Instruction Memory ....................................................................................................................................... 32 7.1.1 Instruction memory map ......................................................................................................................... 32 7.1.2 ...
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PIN FUNCTIONS Because the pin numbers differ depending on the package, see the column for the package to be used in the tables below. 1.1 Description of Pin Functions • • • • Power supply pins Pin Name Pin ...
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Clock and system control pins Pin Name Pin No. 144-pin LQFP 161-pin FBGA CLKIN 20 C6 CLKOUT 25 B6 PLL0 A9,B9,C7,B8 PLL3 HALTS 13 C8 STOPS 11 A10 CSTOP 12 B10 14 ...
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Reset and interrupt pins Pin Name Pin No. 144-pin LQFP 161-pin FBGA RESET 10 C9 INT00 28 C5 INT01 32 C4 INT02 39 C2 INT03 43 D3 INT10 29 D6 INT11 33 A3 INT12 40 C3 ...
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External data memory interface Pin Name Pin No. 144-pin LQFP 161-pin FBGA MA0 to 84, 85, M6,N6,N7,P8, Note MA19 90 to 97, M7,M8,P9,N8, 100 to 107, L8,N9,M9,N10, 111, 112 M10,P11,L10, M11,N11,N12, M13,M12 MD0 to 119,120, J12,H13,G13, ...
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Timer Pin Name Pin No. 144-pin LQFP 161-pin FBGA TIMOUT 68 K3 • • • • Serial interface Pin Name Pin No. 144-pin LQFP 161-pin FBGA ASCK BCLK ASO 70 K4 ASI 76 P3 ...
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Host interface Pin Name Pin No. 144-pin LQFP 161-pin FBGA HA1 63 J3 HA0 62 K1 HCS 61 J2 HRD 64 K2 HWR 66 J4 HRE 65 L2 HWE 67 L1 HD0 ...
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I/O port Pin Name Pin No. 144-pin LQFP 161-pin FBGA ...
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SD card interface ( µ µ µ µ PD77213 only) Pin Name Pin No. 144-pin LQFP 161-pin FBGA SDCLK 112 M12 SDCR 111 M13 SDDAT0 104 L10 SDMON 103 P11 Reserved 105 to 107 M11, N11, ...
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Connection of Unused Pins 1.2.1 Connection of functional pins Connect the unused pins as shown in the table below. Pin Name I/O STOPS, HALTS Output CSTOP Input CLKOUT Output P0 to P15 I/O Note 1 HD0 to HD7 I/O ...
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Connection of non-functional pin Pin name I/O − I.C. − Recommended Connection Leave open. Leave open. Data Sheet U15203EJ3V0DS µ µ µ µ PD77210, 77213 ...
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FUNCTIONAL OUTLINE 2.1 Program Control Unit This unit controls the execution of µ PD77210 Family by executing instructions and controlling branching, loop, interrupts, clock, and standby mode. 2.1.1 CPU control A three-stage pipeline architecture is employed so that all ...
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Instruction memory Of the instruction RAM, 64 words are allocated as interrupt vectors. The µ PD77210 is provided with an instruction RAM of 31.5 Kwords. The µ PD77213 is provided with an instruction RAM of 15.5 Kwords and instruction ...
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Data addressing unit An independent data addressing unit is provided for each of the X and Y data memory spaces. Each data addressing unit has four data pointers (DPn), four index registers (DNn), one module register (DMX or DMY), ...
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General-purpose I/O port (PIO) This is a 16-bit I/O port that can be set to either input or output mode in 1-bit units. The external pins alternate between interrupt pins and host interface pins. By setting the mode of ...
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CLOCK GENERATOR The clock generator generates an internal system clock based on the external clock input from the CLKIN pin and supplies the clock to the µ PD77210 Family. The configuration of the clock generator is as illustrated below. ...
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RESET FUNCTION The device is initialized when a low level of the specified width is input to the RESET pin. 4.1 Hardware Reset The internal circuitry of the µ PD77210 Family is initialized when the RESET pin is asserted ...
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Host boot The boot parameter and instruction code are obtained via the host interface and transferred to the instruction RAM. 5.1.3 Serial boot The boot parameter and instruction code are obtained via the serial interface and transferred to the ...
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Host reboot The instruction code is obtained via the host interface and transferred to the instruction RAM. The entry address is 0x5. Host rebooting is executed by setting the following parameters and then calling this address. • R7L: Number ...
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STANDBY MODE The µ PD77210 Family can be set to either of two standby modes. Each mode can be set by executing the corresponding instruction. The power consumption can be reduced in these modes. 6.1 Halt Mode The halt ...
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MEMORY MAP The µ PD77210 Family employs a Harvard architecture that separates the instruction memory space from the data memory space. 7.1 Instruction Memory 7.1.1 Instruction memory map The instruction memory space consists of 64 Kwords × 32 bits. ...
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Interrupt vector table Addresses 0x200 to 0x23F of the instruction memory are assigned to entry points (vectors) of interrupts. Four instruction addresses are assigned to each interrupt source. Four interrupt sources are assigned to each interrupt vector. There are ...
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Data Memory 7.2.1 Data memory map The data memory space consists of two planes: the X and Y memory spaces, each of which consists of 64 Kwords × 16 bits. The area of 0x8000 to 0xFFFF is a paging ...
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Internal peripherals The internal peripherals are mapped to the internal data memory space. Cautions 1. The register names shown in the above table are not reserved words in either assembler use these names in assembler or ...
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X/Y Memory Address Register Name 0x3854 PMSA1 0x3855 PMS1 0x3856 PMC1 0x3857 PMP1 0x3858 PMSA2 0x3859 PMS2 0x385A PMC2 0x385B PMP2 0x385C PMSA3 0x385D PMS3 0x385E PMC3 0x385F PMP3 0x3860 PMSA4 0x3861 PMS4 0x3862 PMC4 0x3863 PMP4 0x3864 PMSA5 0x3865 ...
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Memory-Mapped Peripherals (3/3) X/Y Memory Address Register Name 0x387C to 0x387F Reserved area 0x3880 ICR0 0x3881 ICR1 0x3882 ICR2 0x3883 ICR3 0x3884 ICR4 0x3885 ICR5 0x3886 ICR6 0x3887 ICR7 0x3888 ICR8 0x3889 ICR9 0x388A ICR10 0x388B ICR11 0x388C to 0x388F ...
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GENERAL-PURPOSE PORT AND INTERRUPT 8.1 General-purpose Port Pins The general-purpose port pins alternate with the interrupt or host interface pins. The configuration of the general-purpose port is illustrated below. Port pin Note not alternate with ...
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INSTRUCTION 9.1 Outline of Instruction One instruction consists of 32 bits. All the instructions, with some exceptions such as branch instructions, are executed with one system clock. The instruction cycle of the µ PD77210 6.25 ns. ...
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Instruction Set and Its Operation Describe an operation in the operation field of each instruction in accordance with the description method of the operation representation format of the instruction. If two or more elements are available, select one of ...
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Modifying data pointer The data pointer is modified only after memory access. The result of the modification becomes valid starting from the instruction that is executed immediately after. The data pointer cannot be modified without the memory access. Example ...
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Instruction Set Instruction Name Mnemonic Multiply add rh*rh’ − rh*rh’ Multiply sub Signed/unsigned rh*rl multiply add ( positive integer format.) Unsigned/unsigned rl*rl’ multiply ...
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Instruction Name Mnemonic Clear CLR (ro) Increment ro’ ro’ − 1 Decrement Absolute value ro’ = ABS (ro) ro’ 1’s complement ro’ = −ro 2’s complement Clip ro’ = CLIP (ro) ...
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Instruction Name Notes *dpx_mod ro’ = *dpy_mod ro ← *dpx, ro’ ← *dpy Parallel load/store ro = *dpx_mod *dpy_mod = rh *dpx_mod = *dpy_mod *dpx_mod = rh *dpy_mod = rh’ *dpx ← rh, ...
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Instruction Name Mnemonic Jump JMP imm Register-to-register JMP dp jump Subroutine call CALL imm Register-to-register CALL dp subroutine call Return RET Interrupt return RETI Repeat REP count Loop LOOP count (Instruction of 2 lines or more) Loop pop LPOP No ...
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ELECTRICAL SPECIFICATIONS = +25° ° ° ° C) Absolute Maximum Ratings (T A Parameter Symbol Supply voltage Input voltage V I Output voltage V O Storage temperature T stg Operating ambient T A temperature Caution ...
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DC Characteristics (Unless otherwise specified, T operating condition range) Parameter Symbol High level input voltage V IHN V IHC V IHS Low level input voltage V ILN V ILC V ILS High level output voltage V OH Low level output ...
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Common Test Criteria of Switching Characteristics RESET P15, TSCK, TSIEN, TSOEN, ASCK, ASIEN, ASOEN Input (other than above) Output 48 0 0.5 EV Test Points 0 0 0.7 ...
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C, with IV AC Characteristics (T A Clock Timing requirements Parameter Symbol Note 1 CLKIN cycle time t cCX CLKIN high level width t wCXH CLKIN low level ...
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Clock I/O timing t wCXH CLKIN Internal clock t dCO t wCO CLKOUT 50 t cCX t wCXL t t cC, cPLL t cCO t wCO Data Sheet U15203EJ3V0DS µ µ µ µ PD77210, 77213 t t rfCX rfCX t ...
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Reset, Interrupt, System Control, Timer Timing requirements Parameter Symbol RESET low level width t w(RL) CSTOP high level width t w(CSTOPH) CSTOP recovery time t rec(CSTOP) INTmn low level width t w (INTL) INTmn recovery time t rec (INT) Notes ...
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Standby mode status output timing Internal clock Execution STOP or Internal status HALT Instruction CSTOP t dSTP STOPS t dHLT HALTS Remarks 1. Internal clock cycle is changed or stopped to be fixed to low level when STOP or HALT ...
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External Data Memory Access Timing requirements Parameter Symbol MD setup time t suMDI MD hold time t hMDI MHOLDRQ setup time t suHRQ MHOLDRQ hold time t hHRQ MWAIT setup time t suWAIT MWAIT hold time t hWAIT Switching characteristics ...
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External data memory access timing (Read) Internal colck t MA0 to MA19 MD0 to MD15 MRD MWAIT MBSTB Remark In the µ PD77213 possible to shift fall timing of MRD pin by cycle unit, by setting of MSHW ...
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Bus arbitration timing Internal colck (Bus busy) t suHRQ MHOLDRQ MHOLDAK MA0 to MA19, MD0 to MD15, MRD, MWR Bus busy Bus idle Bus release t hHRQ t dHAK dMA dMDO dMRD dMWR Hi-Z Data Sheet ...
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General-purpose I/O Port Timing requirements Parameter Symbol Port input setup time t suPI Port input hold time t hPI Switching characteristics Parameter Symbol Port output delay time t dPO General-purpose I/O port timing Internal clock P0 to P15 (output) P0 ...
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Host Interface Timing requirements Parameter Symbol HRD low level width, recovery t wHRD time HWR low level width, t wHWR recovery time HD setup time t suHDI HD hold time t hHDI HA, HCS setup time t suHA HA,HCS hold ...
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Host read interface timing Interanal clock HCS, HA0, HA1 HRD HD0 to HD15 t dRE HRE Host write interface timing Internal clock HCS, HA0, HA1 HWR HD0 to HD15 t dWE HWE 58 t hHA t suHA t wHRD t ...
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Serial Interface (Standard Serial mode/ TDM serial mode) Timing requirements Parameter Symbol ASCK cycle time t cSC ASCK high /low level width t wSC ASCK rise/fall time t rfSC Serial input setup time t suSER Serial input hold time t ...
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Serial output timing 1 t cSC t t wSC wSC ASCK, TSCK t dSER TSORQ t suSER t hSER ASOEN, TSOEN Hi-Z ASO, TSO Note When TDM mode, TSO output value is delay for a bit according to TDM setting ...
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Serial input timing 1 t cSC t t wSC wSC ASCK, TSCK t dSER TSIAK t suSER t hSER ASIEN, TSIEN ASI, TSI Note When TDM mode, TSI input value is delay for a bit according to TDM setting value. ...
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Serial Interface (Audio Serial mode) Timing requirements Parameter Symbol MCLK cycle time t cMC MCLK high/low level width t wMC MCLK rise/fall time t rfMC BCLK cycle time t cBC BCLK high/low level width t wBC BCLK rise/fall time t ...
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Audio serial clock timing t cMC t wMC MCLK Audio serial master mode timing t cBC t t wBC wBC BCLK (output) LRCLK (output) ASO ASI Audio serial slave mode timing t cBC t t wBC wBC BCLK (input) LRCLK ...
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Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in mind the following points when designing your system: • Reinforce the wiring for power supply and ground (if noise is superimposed on the ...
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SD card Interface ( µ µ µ µ PD77213 only) Timing requirements Parameter Symbol SDCR input setup time t suSDCR SDCR input hold time t hSDCR SDDAT input setup time t suSDD SDDAT input hold time t hSDD Switching characteristics ...
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SDCR timing SDCLK t SDCR (Output) SDCR (Input) SDDAT timing SDCLK SDDAT0 (Output) SDDAT0 (Input) Remark The SDMON pin functions alternately as the external data memory interface pin MA13. When accessing a peripheral register related to the SD card interface, ...
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Debugging Interface (JTAG) Timing requirements Parameter Symbol TCK cycle time t cTCK TCK high/low level width t wTCK TCK rise/fall time t rfTCK TDI input setup time t suTDI TDI input hold time t hTDI Input pin setup time t ...
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Debugging interface timing t cTCK t t wTCK wTCK TCK t wTRST TRST TMS, TDI TDO Capture state Update state Remark For details of JTAG, refer to IEEE1149. rfTCK t suTDI t hTDI Valid Valid Valid t dTDO ...
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PACKAGE DRAWINGS 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) 108 109 144 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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PLASTIC FBGA (10x10) E INDEX MARK φ φ Data Sheet U15203EJ3V0DS µ µ ...
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RECOMMENDED SOLDERING CONDITIONS The µ PD77210 Family should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a ...