A1240A-1CQ176B ACTEL [Actel Corporation], A1240A-1CQ176B Datasheet - Page 15

• Manufacturer Part Number: A1240A-1CQ176B
• Description: ACT2 Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

A C T
A 12 40 A Ti m i ng Ch a r ac t e r i s t i cs
(Worst-Case Commercial Conditions, V
Logic Module Propagation Delays
Parameter
t
t
t
t
Predicted Routing Delays
t
t
t
t
t
Sequential Timing Characteristics
t
t
t
t
t
t
t
t
t
t
t
f
Notes:
1.
2.
3.
4.
PD1
CO
GO
RS
RD1
RD2
RD3
RD4
RD8
SUD
HD
SUENA
HENA
WCLKA
WASYN
A
INH
INSU
OUTH
OUTSU
MAX
™
For dual-module macros, use t
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
2 F a m il y F PG A s
Description
Single Module
Sequential Clk to Q
Latch G to Q
Flip-Flop (Latch) Reset to Q
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Flip-Flop (Latch) Data Input
Setup
Flip-Flop (Latch) Data Input
Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active
Pulse Width
Flip-Flop (Latch)
Asynchronous Pulse Width
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
Flip-Flop (Latch) Clock
Frequency
2
PD1
+ t
1
3, 4
RD1
+ t
PDn
, t
CO
CC
+ t
Min.
0.4
0.0
0.8
0.0
4.5
4.5
9.8
0.0
0.4
0.0
0.4
RD1
= 4.75 V, T
‘–2’ Speed
+ t
PDn
v4.0
100.0
Max.
or t
3.8
3.8
3.8
3.8
1.4
1.7
2.3
3.1
4.7
PD1
J
+ t
= 70°C)
RD1
Min.
12.0
0.4
0.0
0.9
0.0
6.0
6.0
0.0
0.4
0.0
0.4
+ t
‘–1’ Speed
SUD
, whichever is appropriate.
Max.
80.0
4.3
4.3
4.3
4.3
1.5
2.0
2.6
3.5
5.4
Min.
15.0
0.5
0.0
1.0
0.0
6.5
6.5
0.0
0.5
0.0
0.5
‘Std’ Speed
Max.
66.0
5.0
5.0
5.0
5.0
1.8
2.3
3.0
4.1
6.3
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15