UPD784927GC NEC [NEC], UPD784927GC Datasheet
UPD784927GC
Related parts for UPD784927GC
UPD784927GC Summary of contents
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PD784927, 784928, 784927Y, 784928Y 16-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The PD784927 and 784928 are members of the NEC 78K/IV Series of microcontrollers equipped with a high- speed, high-performance 16-bit CPU for VCR software servo control. The PD784927Y and 784928Y are based ...
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APPLICATION FIELDS Stationary VCR, video camera, In-TV VCR ORDERING INFORMATION (1) PD784928 subseries Part Number Note PD784927GC- -8EU PD784927GF- -3BA Note PD784928GC- -8EU PD784928GF- -3BA (2) PD784928Y subseries Part Number Note PD784927YGC- -8EU PD784927YGF- -3BA Note PD784928YGC- -8EU PD784928YGF- -3BA ...
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FUNCTION LIST (1/2) Part Number Item Internal ROM capacity 96K bytes Internal RAM capacity 2048 bytes Operating clock 16 MHz (internal clock: 8 MHz) Low frequency oscillation mode : 8 MHz (internal clock: 8 MHz) Low power consumption mode : ...
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FUNCTION LIST (2/2) Part Number Item Analog circuit CTL amplifier RECCTL driver (rewritable) DFG amplifier, DPG amplifier, CFG amplifier DPFG separation circuit (ternary separation circuit) Reel FG comparator (2 channels) CSYNC comparator Interrupt sources 4 levels (programmable), vectored interrupt, macro ...
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PIN CONFIGURATION (Top View) 100-pin plastic LQFP (fine pitch)(14 Note 1 PD784927GC- -8EU , 784928GC- PD784928YGC- -8EU, 784928YGC- 100 Note 2 ...
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QFP (14 20 mm) PD784927GF- -3BA, 784928GF- PD784927YGF- -3BA, 784928YGF- 10099 DFGMON/P64/BUZ 1 DPGMON/P65/HWIN 2 CFGMON/P66/PWM4 3 CTLMON/P67/PWM5 4 P60/STRB/CLO ...
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ANI0-ANI11 : Analog Input Analog Power Supply DD1 DD2 Analog Ground SS1 SS2 AV : Analog Reference Voltage REF BUSY : Serial Busy BUZ : Buzzer Output CFGAMPO : Capstan FG Amplifier ...
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INTERNAL BLOCK DIAGRAM NMI INTERRUPT INTP0-INTP3 CONTROL PWM0-PWM5 SUPER TIMER PTO00-PTO02 UNIT PTO10, PTO11 VREFC REEL0IN REEL1IN CSYNCIN DFGIN DPGIN CFGIN CFGAMPO CFGCPIN CTLOUT1 CTLOUT2 CTLIN RECCTL+ RECCTL- CTLDLY DFGMON DPGMON ANALOG UNIT CFGMON & CTLMON A/D ...
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SYSTEM CONFIGURATION EXAMPLE • Video camera Drum motor M Driver Capstan motor M Driver CTL head Loading motor M Driver Audio/video Composite sync signal signal Video head switch processing Audio head switch circuit Pseudo vertical sync signal Remote Remote controller ...
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Stationary VCR DFG DPG Drum motor M Driver CFG Capstan motor M Driver CTL head Loading motor M Driver Reel FG0 Driver M Reel motor M Driver Reel FG1 Note Pins SCL and SDA are provided for the PD784928Y ...
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DIFFERENCE BETWEEN PD784928 SUBSERIES AND 784928Y SUBSERIES .................... 12 2. PIN FUNCTION ............................................................................................................................... 13 2.1 Port Pins ................................................................................................................................................ 2.2 Pins Other Than Port Pins .................................................................................................................. 2.3 I/O Circuits of Pins and Processing of Unused Pins ...................................................................... 3. INTERNAL BLOCK ...
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DIFFERENCE BETWEEN PD784928 SUBSERIES AND 784928Y SUBSERIES The PD78F4928 and 78F4928Y are based on the PD784927 and 784927Y and are provided with a 128K-byte flash memory instead of a mask ROM. Table 1-1 shows the differences between the products ...
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PIN FUNCTION 2.1 Port Pins Pin Name I/O Shared with: P00-P07 I/O Real-time output port P20 Input NMI P21-P23 INTP0-INTP2 P30-P32 I/O PTO00-PTO02 P33 SI2/BUSY P34 SO2 P35 SCK2 P36, P37 PWM1, PWM0 P40-P47 I/O P50-P57 I/O P60 I/O ...
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Pins Other Than Port Pins (1/2) Pin Name I/O Shared with: REEL0IN Input P102/INTP3 REEL1IN P101 DFGIN DPGIN P100 CFGIN CSYNCIN P103 CFGCPIN CFGAMPO Output PTO00 Output P30 PTO01 P31 PTO02 P32 PTO10 P86 PTO11 P87 PWM0 Output P37 ...
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Pins Other Than Port Pins (2/2) Pin Name I/O Shared with: VREFC — DFGMON Output P64/BUZ DPGMON P65/HWIN CFGMON P66/PWM4 CTLMON P67/PWM5 NMI Input P20 INTP0-INTP2 Input P21-P23 INTP3 Input P102/REEL0IN KEY0-KEY4 Input P91-P95 CLO Output P60/STRB BUZ Output ...
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I/O Circuits of Pins and Processing of Unused Pins Table 2-1 shows the types of the I/O circuits of the respective pins and processing of the unused pins. Figure 2-1 shows the circuits of the respective types. Table 2-1. ...
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Table 2-1. I/O Circuits of Respective Pins and Processing of Unused Pins (2/2) Pin I/O Circuit Type P100/DPGIN — P101/REEL1IN P102/REEL0IN/INTP3 P103/CSYNCIN P110/ANI8-P113/ANI11 9 RECCTL+, RECCTL– — DFGIN — CFGIN, CFGCPIN CTLOUT1 — CTLOUT2 — CFGAMPO — CTLIN — VREFC ...
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Figure 2-1. I/O Circuits of Respective Pins Type 2 IN Schmitt trigger input with hysteresis characteristics Type 2 P-ch IN Schmitt trigger input with hysteresis characteristics Type 5-A Pull-up enable V DD Data P-ch Output N-ch disable Input ...
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INTERNAL BLOCK FUNCTION 3.1 CPU Registers 3.1.1 General-purpose registers The PD784927 has eight banks of general-purpose registers. One bank consists of sixteen 8-bit general-purpose registers. Two of these 8-bit registers can be used in pairs as a 16-bit register. ...
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Other CPU registers (1) Program counter The program counter of the PD784927 is 20 bits wide. The value of the program counter is automatically updated as the program is executed (2) Program status word This is a ...
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Memory Space A memory space of 1M bytes can be accessed. The mapping of the internal data area (special function registers and internal RAM) can be selected by using the LOCATION instruction. The LOCATION instruction must be always executed ...
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Figure 3-2. Memory Map of PD784927, 784927Y When LOCATION 0H instruction is executed FFFFFH 0FEFFH Cannot be used 0FE80H 0FE7FH 18000H 17FFFH Internal ROM (32768 bytes) 0FE3BH 10000H 0FFFFH Special function registers (SFRs) 0FE06H 0FFDFH Note 1 0FFD0H (256 bytes) ...
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Figure 3-3. Memory Map of PD784928, 784928Y When LOCATION 0H instruction is executed FFFFFH 0FEFFH Cannot be used 0FE80H 0FE7FH 20000H 1FFFFH Internal ROM (65536 bytes) 0FE3BH 10000H 0FFFFH Special function registers (SFRs) 0FE06H 0FFDFH Note 1 0FFD0H (256 bytes) ...
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Special Function Registers (SFRs) Special function registers are assigned special functions and mapped to a 256-byte space of addresses FF00H through FFFFH. These registers include mode registers and control registers that control the internal peripheral hardware units. Caution Do ...
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Table 3-1. Special Function Registers (1/5) Address Special Function Register (SFR) Name FF00H Port 0 FF02H Port 2 FF03H Port 3 FF04H Port 4 FF05H Port 5 FF06H Port 6 FF07H Port 7 FF08H Port 8 FF09H Port 9 FF0AH ...
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Table 3-1. Special Function Registers (2/5) Address Special Function Register (SFR) Name FF38H Timer control register 0 FF39H Timer control register 1 FF3AH Timer control register 2 FF3BH Timer control register 3 FF3CH Timer counter 3 FF3DH Timer control register ...
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Table 3-1. Special Function Registers (3/5) Address Special Function Register (SFR) Name FF71H PWM control register 1 FF72H PWM0 modulo register FF73H PWM2 modulo register FF74H PWM1 modulo register FF75H PWM3 modulo register FF76H PWM5 modulo register FF77H PWM4 modulo ...
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Table 3-1. Special Function Registers (4/5) Address Special Function Register (SFR) Name FFA4H VISS detection circuit up/down counter register FFA5H VUDC value setting register FFA6H Key interrupt control register FFA7H VISS pulse pattern setting register FFA8H In-service priority register FFAAH ...
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Table 3-1. Special Function Registers (5/5) Address Special Function Register (SFR) Name FFE7H Interrupt control register (INTCR01) FFE8H Interrupt control register (INTCR02) FFE9H Interrupt control register (INTCR11) FFEAH Interrupt control register (INTCPT1) FFEBH Interrupt control register (INTCR20) Note 1 FFECH ...
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Ports The PD784927 is provided with the ports shown in Figure 3-3. Table 3-2 shows the function of each port. Port 0 Port 2 Port 3 Port 4 Port 5 Name Pin Name Port 0 P00-P07 Can be set ...
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Real-Time Output Port A real-time output port consists of a port output latch and a buffer register (refer to Figure 3-5). The function to transfer the data prepared in advance in the buffer register to the output latch when ...
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Figures 3-6 and 3-7 show the block diagrams of RTP0 and RTP8. Figure 3-8 shows the types of RTP output trigger sources. Figure 3-6. Block Diagram of RTP0 8 Real-time output port 0 control register (RTPC) INTP0 Output trigger INTCR01 ...
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Figure 3-8. Types of RTP Output Trigger Sources INTP0 TM0 CR00 Interrupt and CR01 timer output CR02 TM1 CR10 Interrupt and timer output CR11 Capture CR12 Interrupt CR13 TM5 CR50 Interrupt Data Sheet U12255EJ2V0DS00 PD784927, 784928, 784927Y, 784928Y Real-time output ...
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RTP80 can output low-level, high-level, and high-impedance values real-time. Because RTP80 can superimpose a horizontal sync signal, it can be used to create pseudo vertical sync signal. When RTP80 is set in the pseudo V SYNC occurs. Figure 3-9 shows ...
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Super Timer Unit The PD784927 is provided with a super timer unit that consists of the timers, and VCR special circuits such as a VISS detection circuit and a V separation circuit, etc., shown in Table 3-5. SYNC Table ...
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Timer 0 unit Timer 0 unit creates head switching signal and pseudo V drum motor. This unit consists of an event counter (EC: 8 bits), compare registers (ECC0 through ECC3), a timer (TM0: 16 bits), and compare registers (CR00 ...
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Figure 3-10. Block Diagram of Super Timer Unit (TM0, FRC, TM1) DPGIN Divider Selector Writes 00H to EC Clear DFGIN EC ECC3 F/F ECC2 ECC1 F/F ECC0 V separation SYNC circuit CSYNCIN Mask REEL0IN REEL1IN Clear CFGIN EDV EDVC PBCTL ...
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Timer 2 unit Timer 2 unit is a general-purpose 16-bit timer unit. This unit consists of a timer (TM2) and a compare register (CR20). The timer is cleared when the TM2-CR20 coincidence signal occurs, and at the same time, ...
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Up/down counter unit The up/down counter unit is a counter that realizes a linear time counter. This unit consists of an up/down counter (UDC) and a compare register (UDCC). The up/down counter counts up the rising edges of PBCTL ...
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Figure 3-16. Block Diagram of 8-Bit PWM Output Unit PWM2 8-bit comparator 8-bit comparator 16 MHz PWM counter (9) VISS detection circuit Figure 3-17. Block Diagram of VISS Detection Circuit PBCTL CFG signal f /16 CLK f /64 CLK f ...
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V separation circuit SYNC Figure 3-18. Block Diagram signal SYNC f /4 CLK (8-bit up/down f /8 CLK (8-bit compare 3.7 Serial Interface The PD784927 is provided with the serial interfaces shown in Table 3-6. Data ...
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Serial interface channels 1, 2 Figure 3-19. Block Diagram of Serial Interface Channel SIn /BUSY SOn SCKn STRB Remark The circuits enclosed in the broken line are provided to serial interface channel 2 ...
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Serial interface channel 3 ( PD784928Y subseries only) This channel transfers 8-bit data with multiple devices using two lines: serial clock (SCL) and serial data bus (SDA conforms to the I C bus format, and can output ...
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A/D Converter The PD784927Y has an analog-to-digital (A/D) converter with 12 multiplexed analog inputs (ANI0 through ANI11). This A/D converter is of successive approximation type, and the conversion result is held by an 8-bit A/D conversion result register (ADCR) ...
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Figure 3-21. Block Diagram of A/D Converter ANI0 Sample & hold circuit ANI1 ANI2 ANI3 . . . . . . ANI11 Conversion TM0-CR01 coincidence trigger TM0-CR02 coincidence TM1-CR13 coincidence TM5-CR50 coincidence Trigger enable Trigger source select register 1 (TRGS1) ...
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CTL amplifier/RECCTL driver The CTL amplifier is used to amplify the playback control (PBCTL) signal that is reproduced from the CTL signal recorded on a VCR tape. The gain of the CTL amplifier is set by the gain control ...
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DPG amplifier, DFG amplifier, and DFPG separation circuit The DPG amplifier converts the drum PG (DPG) signal that indicates the phase information of the drum motor into a logic signal. The DFG amplifier amplifies the drum FG (DFG) signal ...
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CFG amplifier The CFG amplifier amplifies the capstan FG (CFG) signal that indicates the speed information of the capstan motor. This amplifier consists of an operational amplifier and a comparator. The gain of the operational amplifier is set by ...
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CSYNC comparator The CSYNC comparator converts the COMPSYNC signal into a logic signal. Figure 3-26. Block Diagram of COMPSYNC Comparator AMPM0.0 COMP signal SYNC CSYNCIN (6) Reference amplifier The reference amplifier generates a reference voltage (V comparators of the ...
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Analog circuit monitor function This function is to output the following signals to port pins, and is mainly used for debugging. • Comparator output of CTL amplifier • Comparator output of CFG amplifier • Comparator output of DPG amplifier ...
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Clock Output Function The PD784927 can output a square wave (with a duty factor of 50%) to the P60/STRB/CLO pin as the operating clock for the peripheral devices or other microcomputers. To enable or disable the clock output, and ...
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Buzzer Output Function The BUZ signal can be superimposed on P61 or P64. The buzzer output frequency can be generated from the subsystem clock frequency or main system clock frequency. Figure 3-31 shows the block diagram of the BUZ ...
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INTERNAL/EXTERNAL CONTROL FUNCTION 4.1 Interrupt Function The PD784927 has as many as 32 interrupt sources, including internal and external sources. For 28 sources, a high-speed interrupt processing mode such as context switching or macro service can be specified by ...
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Interrupt Interrupt Request Source Request Priority Name Type Reset — RESET RESET pin input Non- — NMI NMI pin input edge maskable Maskable 0 INTP0 INTP0 pin input edge 1 INTCPT3 EDVC output signal (CPT3 capture) 2 INTCPT2 DFGIN pin ...
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Figure 4-1. Differences in Operation Depending on Interrupt Processing Mode Main Macro service Macro service routine processing Context Main Note 2 Note 1 routine switching Vectored Main Note 4 Note 1 routine interrupt Main Vectored interrupt Note 4 routine Interrupt ...
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Vectored interrupt When an interrupt request is acknowledged, an interrupt processing program is executed according to the data stored in the vector table area (the first address of the interrupt processing program created by the user). In addition, four ...
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Macro service The macro service is a function to transfer data between the memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR and directly transfers the data. ...
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Macro service type A When an interrupt request occurs, data is transferred from an 8-/16-bit SFR to memory (byte/word) or from memory (byte/word 8-/16-bit SFR. Data is transferred the number of times set in advance by the ...
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Application example of macro service (1) Automatic transfer/reception of serial interface Automatic transfer/reception of 3-byte data by serial interface channel 1 Setting of macro service register: compound data transfer mode (exchange mode) Macro service channel Macro service control word ...
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Reception operation of serial interface Transfer of receive data by serial interface channel 1 (16 bytes) Setting of macro service mode register: macro service type A (1-byte data transfer from SFR to memory) FE7FH FE2EH SIO1 SI1 (FF85H) 60 ...
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VISS detection operation Setting of macro service mode register: data pattern identification mode (with multiplication, 8-byte compari- son) High-order address Macro service counter (MSC = FFH) FE50H SFR pointer 2 (SFRP2 = 56H) Coefficient (6EH: 43%) SFR pointer 3 ...
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Standby Function The standby function is to reduce the power consumption of the chip and is used in the following modes: Mode HALT mode STOP mode Low power consumption mode Low power consumption HALT mode These modes are programmable. ...
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Figure 4-5. Relations among NMI, Watch Interrupt, and Key Interrupt When STOP Mode Is Released INTM0.0 NMI INTP1 INTP2 KEY0 KEY1 KEY2 KEY3 KEY4 Mask KEYC.6 Mask KEYC.5 Mask KEYC.4 PD784927, 784928, 784927Y, 784928Y Latch Clear S Q KEYC.7 R ...
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Figure 4-6. Block Diagram of Clock Generation Circuit PD784927 Low-frequency X1 Main oscillation mode system f XX clock Normal mode oscillation circuit 1 MHz or 8 MHz Oscillation stop From standby control block XT1 Subsystem f clock XT ...
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Reset Function When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset status). During the reset period, oscillation of the system clock is unconditionally stopped, so that the ...
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INSTRUCTION SET (1) 8-bit instructions (( ): combination realized by using MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, ...
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AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW 2nd Operand # word AX rp ...
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WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP 2nd Operand # imm24 WHL 1st Operand WHL (MOVG) (MOVG) (MOVG) (ADDG) (ADDG) (ADDG) (SUBG) (SUBG) (SUBG) rg MOVG (MOVG) MOVG ...
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Call/return and branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Symbol Supply voltage DD1 AV DD2 AV SS1 AV SS2 Input voltage VI Analog input voltage V IAN (ANI0-ANI11) Output voltage V O Low-level output ...
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Oscillator Characteristics (main clock) (T Resonator Recommended Circuit Crystal resonator Oscillator Characteristics (subclock) (T Resonator Recommended Circuit Crystal resonator XT1 XT2 V C1 Caution When using the main system clock and subsystem clock oscillator, wire the portion ...
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DC Characteristics (T = – Parameter Symbol Low-level input voltage V Pins other than those listed in Note 1 below IL1 V Pins listed in Note 1 below IL2 V X1, X2 IL3 High-level input ...
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AC Characteristics CPU and peripheral circuit operation clock (T Parameter Symbol CPU operation clock cycle time Peripheral operation clock cycle time Serial interface (1) SIOn – Parameter Symbol ...
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I C bus mode ( PD784928Y subseries only) Parameter Symbol SCL clock frequency Bus free time (between stop and start conditions) Note 1 Hold time SCL clock low-level width SCL clock high-level width Start/restart condition setup time Data hold ...
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Other operations (T = – Parameter Symbol Timer input signal low-level width Timer input signal high-level width Timer input signal valid edge input cycle CSYNCIN low-level width CSYNCIN high-level width Digital noise Rejected pulse width ...
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Clock output operation (T = – Parameter Symbol CLO cycle time CLO low-level width CLO high-level width CLO rise time CLO fall time Remarks 1. n: system clock division 1/f CLK Data ...
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VREF amplifier ( Parameter Symbol Reference voltage Charge current Note RECCTL+, RECCTL–, CFGIN, CFGCPIN, DFGIN, DPGIN, CSYNCIN, REEL0IN, REEL1IN CTL amplifier ( ...
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CFG amplifier (AC coupling Parameter Symbol Voltage gain 1 Voltage gain 2 CFGAMPO High-level output current CFGAMPO Low-level output current High comparator voltage Low comparator voltage Duty accuracy Note The conditions include the following ...
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DPG amplifier (AC coupling Parameter Symbol Voltage gain High comparator voltage Low comparator voltage Caution When both the SELDPGHL0 and SELDPGHL1 are set to 0, the DPG amplifier is not used. Therefore, be sure ...
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Timing waveform AC timing test point 0 2 0.8 V Serial transfer timing (SIOn WSKL SCKn t CYSK SIn SOn 80 PD784927, 784928, 784927Y, 784928Y 0.8 V Test point t ...
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Serial transfer timing (SIO2 only) No busy processing t t WSKL WSKH SCK2 CYSK BUSY Active high STRB Continuation of busy processing t t WSKL WSKH SCK2 CYSK BUSY Active high STRB End of ...
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I C bus mode ( PD784928Y subseries only) t LOW t R SCL DAT STA SDA t BUF Stop Start condition condition 82 PD784927, 784928, 784927Y, 784928Y HIGH ...
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Super timer unit input timing When DFGIN, CFGIN, DPGIN, 0.8 V REEL0IN, or REEL1IN logic level is input 0.8 V When CSYNCIN logic level is input Interrupt request input timing 0.8 V NMI DD 0 INTP0, INTP3 0.8 ...
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Reset input timing RESET Clock output timing 0 CLO 0 CLR 84 PD784927, 784928, 784927Y, 784928Y t WRSL 0 CLH t CLF t CLL t CYCL Data Sheet U12255EJ2V0DS00 ...
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PACKAGE DRAWING 100 PIN PLASTIC LQFP (FINE PITCH) (14 14 100 NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. Remark ...
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PLASTIC QFP (14x20 100 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. Remark The package dimensions and materials of ES versions ...
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RECOMMENDED SOLDERING CONDITIONS Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, consult NEC. ...
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APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for developing systems using the PD784927. Refer to (5) Cautions when the development tools are used. (1) Language processing software RA78K4 78K/IV series common assembler package CC78K4 78K/IV series common ...
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When using the IE-784000-R in-circuit emulator IE-784000-R 78K/IV series common in-circuit emulator IE-70000-98-IF-C Interface adapter necessary when a PC-9800 series computer (except notebook personal computer) is used as host machine (C bus compatible) IE-70000-PC-IF-C Interface adapter necessary when an ...
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Cautions when the development tools are used • The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784928. • The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784928. • FL-PR2, FL-PR3, FA-100GC, and ...
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APPENDIX B. RELATED DOCUMENTS Device-related documents Document PD784928, 784928Y Subseries User’s Manual - Hardware PD784927, 784928, 784927Y, 784928Y Data Sheet PD784928 Subseries Special Function Register Table PD78F4928 Preliminary Product Information PD784928Y Subseries Special Function Register Table PD78F4928Y Preliminary Product Information ...
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Embedded software-related documents (User’s Manual) Document 78K/IV Series Real-Time OS 78K/IV Series OS, MX78K4 Other documents Document SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control ...
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PD784927, 784928, 784927Y, 784928Y Data Sheet U12255EJ2V0DS00 93 ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...
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The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without ...