74AUP2G132GT,115 NXP Semiconductors, 74AUP2G132GT,115 Datasheet - Page 9

• Manufacturer Part Number: 74AUP2G132GT,115
• Description: IC NAND SCHMITT DUAL 8-XSON
• Manufacturer: NXP Semiconductors
• Series: 74AUPr

Specifications of 74AUP2G132GT,115

• Number Of Circuits: 2
• Package / Case: 8-XSON
• Logic Type: NAND Gate - Schmitt Trigger
• Number Of Inputs: 2
• Current - Output High, Low: 4mA, 4mA
• Voltage - Supply: 0.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: AUP
• High Level Output Current: - 4 mA
• Low Level Output Current: 4 mA
• Propagation Delay Time: 22.6 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0.8 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74AUP2G132GT-G; 74AUP2G132GT-G; 935280733115

NXP Semiconductors
13. Waveforms
Table 9.
Table 10.
[1]
74AUP2G132
Product data sheet
Supply voltage
V
0.8 V to 3.6 V
Supply voltage
V
0.8 V to 3.6 V
Fig 8.
Fig 9.
CC
CC
For measuring enable and disable times R
Measurement points are given in
Logic levels: V
The data input (nA or nB) to output (nY) propagation delays
Test data is given in
Definitions for test circuit:
R
C
R
V
Load circuitry for switching times
L
L
T
EXT
Measurement points
Test data
= Load resistance.
= Load capacitance including jig and probe capacitance.
= Termination resistance should be equal to the output impedance Z
= External voltage for measuring switching times.
Load
C
5 pF, 10 pF, 15 pF and 30 pF
L
OL
and V
Table
Output
V
0.5 × V
OH
M
10.
are typical output voltage levels that occur with the output load.
CC
nA, nB input
nY output
Table
L
All information provided in this document is subject to legal disclaimers.
G
= 5 kΩ, for measuring propagation delays, setup and hold times and pulse width R
V
V
V
V
OH
9.
OL
T+
T−
V I
Rev. 4 — 4 November 2010
Input
V
0.5 × V
R
5 kΩ or 1 MΩ
R T
M
L
V
t
[1]
PHL
M
DUT
V
CC
CC
V
M
V O
Low-power dual 2-input NAND Schmitt trigger
V
t
open
C L
o
PLH
001aac521
EXT
of the pulse generator.
t
V
PLH
EXT
, t
V
V
I
CC
001aaj265
PHL
5 kΩ
R L
t
GND
PZH
74AUP2G132
, t
PHZ
t
≤ 3.0 ns
r
= t
© NXP B.V. 2010. All rights reserved.
f
t
2 × V
PZL
, t
CC
PLZ
L
= 1 MΩ.
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