BS85B12-3 HOLTEK [Holtek Semiconductor Inc], BS85B12-3 Datasheet - Page 71

• Manufacturer Part Number: BS85B12-3
• Description: Touch Key Flash Type 8-Bit MCU with LCD/LED Driver
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

BS85B12-3/BS85C20-3
Touch Key Flash MCU with LCD/LED Driver
Rev. 1.00
Bit 7~2
Bit 1~0
Bit 7
Bit 6~4
Bit 3
Name
Name
POR
POR
R/W
R/W
Bit
Bit
TMnAH Register
TMnC0 Register
TnPAU
R/W
unimplemented, read as 0
TMn 10-bit CCRA bit 9 ~ bit 8
TnPAU: TMn Counter Pause Control
The counter can be paused by setting this bit high. Clearing the bit to zero restores normal
counter operation. When in a Pause condition the TM will remain powered up and continue to
consume power. The counter will retain its residual value when this bit changes from low to high
and resume counting from this value when the bit changes to a low value again.
TnCK2~TnCK0: Select TMn Counter clock
These three bits are used to select the clock source for the TM. Selecting the Reserved clock
input will effectively disable the internal counter. The external pin clock source can be chosen to
be active on the rising or falling edge. The clock source f
f
TnON: TMn Counter On/Off Control
This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to
run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting
and turn off the TM which will reduce its power consumption. When the bit changes state from
low to high the internal counter value will be reset to zero, however when the bit changes from
high to low, the internal counter will retain its residual value.
If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial
condition, as specified by the TnOC bit, when the TnON bit changes from low to high.
7
7
0
TBC
0: run
1: pause
000: f
001: f
010: f
011: f
100: f
101: undefined
110: TCKn rising edge clock
111: TCKn falling edge clock
0: Off
1: On
are other internal clocks, the details of which can be found in the oscillator section.
H
SYS
SYS
H
TBC
/64
/16
/4
TnCK2
R/W
6
6
0
TnCK1
R/W
5
5
0
TnCK0
R/W
65
4
4
0
TnON
R/W
3
3
0
SYS
is the system clock, while f
TnRP2
R/W
2
2
0
TnRP1
R/W
R/W
D9
1
0
1
0
February 1, 2011
H
TnRP0
and
R/W
R/W
D8
0
0
0
0