74HCT132DB,118 NXP Semiconductors, 74HCT132DB,118 Datasheet - Page 2

• Manufacturer Part Number: 74HCT132DB,118
• Description: IC TRIGGER NAND QUAD 2-IN 14SSOP
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT132DB,118

• Number Of Circuits: 4
• Package / Case: 14-SSOP
• Logic Type: NAND Gate - Schmitt Trigger
• Number Of Inputs: 2
• Current - Output High, Low: 5.2mA, 5.2mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Product: NAND
• Logic Family: HCT
• High Level Output Current: - 4 mA
• Low Level Output Current: 4 mA
• Propagation Delay Time: 17 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74HCT132DB-T; 74HCT132DB-T; 935187300118

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT132 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT132 contain four 2-input NAND gates which accept standard input signals. They are capable of
transforming slowly changing input signals into sharply defined, jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The difference between the positive voltage
V
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
September 1993
SYMBOL
t
C
C
T
PHL
Output capability: standard
I
Quad 2-input NAND Schmitt trigger
I
PD
CC
f
f
C
V
For HCT the condition is V
and the negative voltage V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
= input frequency in MHz
L
category: SSI
= output frequency in MHz
PLH
(C
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
D
L
= C
V
amb
CC
PD
2
= 25 C; t
PARAMETER
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
V
f
o
CC
) = sum of outputs
2
f
r
i
= t
I
= GND to V
I
f
T
= GND to V
= 6 ns
(C
is defined as the hysteresis voltage V
L
V
CC
2
CC
CC
f
o
) where:
1.5 V
2
.
CONDITIONS
C
notes 1 and 2
L
D
= 15 pF; V
in W):
H
.
CC
= 5 V 11
3.5
24
HC
TYPICAL
74HC/HCT132
Product specification
17
3.5
20
HCT
ns
pF
pF
UNIT