bc41b143a07 ETC-unknow, bc41b143a07 Datasheet - Page 80

• Manufacturer Part Number: bc41b143a07
• Description: Single Chip Bluetooth
• Manufacturer: ETC-unknow

CS-101564-DSP12
Name
-
SLAVE_MODE_EN
SHORT_SYNC_EN
-
SIGN_EXTEND_EN
LSB_FIRST_EN
TX_TRISTATE_EN
TX_TRISTATE_RISING_EDGE_EN
SYNC_SUPPRESS_EN
GCI_MODE_EN
MUTE_EN
48M_PCM_CLK_GEN_EN
LONG_LENGTH_SYNC_EN
-
MASTER_CLK_RATE
ACTIVE_SLOT
Bit Position
[20:16]
[22:21]
[26:23]
12
10
11
0
1
2
3
4
5
6
7
8
9
Production Information
© CSR plc 2003-2007
Description
Set to 0
0 = master mode with internal generation of PCM_CLK and
PCM_SYNC.
1 = slave mode requiring externally generated PCM_CLK
and PCM_SYNC.
0 = long frame sync (rising edge indicates start of frame).
1 = short frame sync (falling edge indicates start of frame).
Set to 0.
0 = padding of 8 or 13-bit voice sample into a 16-bit slot by
inserting extra LSBs. When padding is selected with 13-bit
voice sample, the 3 padding bits are the audio gain setting;
with 8-bit sample the 8 padding bits are zeroes.
1 = sign-extension.
0 = MSB first of transmit and receive voice samples.
1 = LSB first of transmit and receive voice samples.
0 = drive PCM_OUT continuously.
1 = tri-state PCM_OUT immediately after falling edge of
PCM_CLK in the last bit of an active slot, assuming the next
slot is not active.
0 = tri-state PCM_OUT immediately after falling edge of
PCM_CLK in last bit of an active slot, assuming the next slot
is also not active.
1 = tri-state PCM_OUT after rising edge of PCM_CLK.
0 = enable PCM_SYNC output when master.
1 = suppress PCM_SYNC whilst keeping PCM_CLK running.
Some CODECS utilise this to enter a low power state.
1 = enable GCI mode
1 = force PCM_OUT to 0
0 = set PCM_CLK and PCM_SYNC generation via DDS from
internal 4MHz clock.
1 = set PCM_CLK and PCM_SYNC generation via DDS from
internal 48MHz clock.
0 = set PCM_SYNC length to 8 PCM_CLK cycles.
1 = set length to 16 PCM_CLK cycles.
Only applies for long frame sync and with
48M_PCM_CLK_GEN_EN set to 1.
Set to 0b00000
Selects 128 (0b01), 256 (0b00), 512 (0b10) kHz PCM_CLK
frequency when master and 48M_PCM_CLK_GEN_EN (bit
11) is low.
Default is 0001. Ignored by firmware.
Device Terminal Descriptions
Page 80 of 97