VN16218L2 VAISH [Vaishali Semiconductor], VN16218L2 Datasheet - Page 8

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VN16218L2

Manufacturer Part Number
VN16218L2
Description
2.5 Gigabit SERDES Transceiver
Manufacturer
VAISH [Vaishali Semiconductor]
Datasheet
VN16218
Table 10. DC Electrical Specifications for LVTTL Inputs
T
Table 11. Transmitter Timing Characteristics
T
Note:
The transmitter latency, as shown in Figure 6, is defined as the time between the latching in of the parallel data word (as triggered by
the rising edge of the transmit byte clock, TBC) and the transmission of the first serial bit of that parallel word (defined by the rising
edge of the first bit transmitted).
2001-11-09
A
Symbol
V
V
A
t
t
t_txlat
setup
hold
Vaishali Semiconductor
IH
IL
Symbol
= 0 C to +70 C, VDDT = 3.15 V to 3.45 V. VDD = 1.7V to 1.9V
= 0 C to +70 C, VDDT = 3.15 V to 3.45 V, VDD = 1.7V to 1.9V
[1]
T19:0
Input High Voltage Level
Input Low Voltage Level
TBC
Setup Time to Rising Edge of TBC
Hold Time to Rising Edge of TBC
Transmitter Latency
DOUT
T19:0
TBC
T15 T16 T17 T18 T19 T0 T1 T2
747 Camden Avenue, Suite C
DATA
DATA
Parameter
Parameter
t
t
SETUP
SETUP
Figure 5. Transmitter Section Timing
Figure 6. Transmitter Latency
DATA
DATA
www.vaishali.com
t
t
DATA BYTE B
HOLD
HOLD
DATA BYTE A
DATA
DATA
Campbell
Page 8
t_TXLAT
1.5
1.0
T16 T17 T18 T19 T0 T1 T2 T3 T4 T5
Min.
CA 95008
Conditions
DATA
DATA
3.5
0.8ns+
8.5 bits
Typ.
Ph. 408.377.6060
DATA
DATA
DATA BYTE B
DATA BYTE C
Max.
2.00
Min.
Advance Information
DATA
DATA
Fax 408.377.6063
Typ.
nsec
nsec
nsec
Unit
MDSN-0003-00
1.4 V
0.80
Max.
1.4 V
1.4 V
2.0 V
2.0 V
0.8 V
0.8 V
V
V
Unit

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