VN16218L2 VAISH [Vaishali Semiconductor], VN16218L2 Datasheet - Page 9

• Manufacturer Part Number: VN16218L2
• Description: 2.5 Gigabit SERDES Transceiver
• Manufacturer: VAISH [Vaishali Semiconductor]

VN16218
Table 12. Receiver Timing Characteristics
TA = 0 C to +70 C, Vcc = 3.15 V to 3.45 V
Notes:
1. This is the recovery for input phase jumps.
2. The receiver latency as shown in Figure 8, is defined as the time between receiving the first serial bit of a parallel
2001-11-09
b_sync
f_lock
t
t
t
t
T_rxlat
SETUP
HOLD
DUTY
A-B
Vaishali Semiconductor
Symbol
data word (defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the
rising edge of the receive byte clock, either RBC or RBCN).
COM_DET
[2]
[1]
RBCN
R19:0
RBC
DIN
R19:0
RBC/RBCN
Bit Sync Time
Frequency Lock at Powerup
Data Setup Before Rising Edge of RBC,RBCN
Data Hold After Rising Edge of RBC,RBCN
RBC,RBCN Duty Cycle
RBC,RBCN Skew
Receiver Latency
t
SETUP
R15 R16 R17 R18
DATA BYTE C
747 Camden Avenue, Suite C
K28.5
R19
Figure 7. Receiver Section Timing
Parameter
Figure 8. Receiver Latency
t
HOLD
R0
DATA
R1
DATA BYTE A
R2
www.vaishali.com
DATA BYTE D
Campbell
Page 9
DATA
t_rxlat
R16 R17 R18 R19
CA 95008
DATA
2.5
1.5
40
7.5
Min.
Ph. 408.377.6060
t
A-B
DATA
22.4
28.0
Typ.
DATA BYTE D
R2 R3 R4
Advance Information
2500
500
60
8.5
Max.
Fax [phone]
R5
bits
nsec
nsec
%
nsec
nsec
bits
Unit
s
2.0 V
0.8 V
2.0 V
0.8 V
1.4 V
1.4 V
MDSN-0003-00
1.4 V