74LVC2G240GM,125 NXP Semiconductors, 74LVC2G240GM,125 Datasheet - Page 9
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74LVC2G240GM,125
Manufacturer Part Number
74LVC2G240GM,125
Description
IC INVERTER DUAL 4-INPUT 8QFN
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet
1.74LVC2G240DC125.pdf
(22 pages)
Specifications of 74LVC2G240GM,125
Logic Type
Inverter
Number Of Inputs
1
Number Of Circuits
2
Current - Output High, Low
32mA, 32mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-XQFN
Logic Family
LVC
Number Of Channels Per Chip
2
Polarity
Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Low Level Output Current
32 mA
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
2 / 2
Output Type
3-State
Propagation Delay Time
3 ns at 2.7 V, 2.5 ns at 3 V to 3.6 V, 2 ns at 4.5 V to 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVC2G240GM-G
74LVC2G240GM-G
935282651125
74LVC2G240GM-G
935282651125
NXP Semiconductors
12. Waveforms
Table 9.
74LVC2G240
Product data sheet
Supply voltage
V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
4.5 V to 5.5 V
Fig 7.
Fig 8.
CC
Measurement points are given in
Logic levels: V
Measurement points are given in
Logic levels: V
The data input (nA) to output (nY) propagation delays
3-state enable and disable times
Measurement points
OL
OL
and V
and V
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
nOE input
OH
output
output
OH
are typical output voltage levels that occur with the output load.
are typical output voltage levels that occur with the output load.
nY output
Input
V
0.5 × V
0.5 × V
1.5 V
1.5 V
0.5 × V
nA input
M
GND
GND
V
V
Table
V
Table
OH
CC
OL
GND
V
V
V
All information provided in this document is subject to legal disclaimers.
I
OH
OL
V
CC
CC
CC
I
9.
9.
Rev. 5 — 15 September 2010
enabled
V
outputs
M
t
PLZ
t
V
PHZ
M
V
M
Output
V
0.5 × V
0.5 × V
1.5 V
1.5 V
0.5 × V
t
V
PHL
M
X
V
Y
CC
CC
CC
disabled
outputs
V
V
M
M
Dual inverting buffer/line driver; 3-state
t
t
PZL
PZH
t
PLH
mna960
V
V
V
V
V
V
X
OL
OL
OL
OL
OL
V
+ 0.15 V
+ 0.15 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
M
V
M
outputs
enabled
mna961
74LVC2G240
V
V
V
V
V
V
© NXP B.V. 2010. All rights reserved.
Y
OH
OH
OH
OH
OH
− 0.15 V
− 0.15 V
− 0.3 V
− 0.3 V
− 0.3 V
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