CY2DP818-2_08 CYPRESS [Cypress Semiconductor], CY2DP818-2_08 Datasheet - Page 2

• Manufacturer Part Number: CY2DP818-2_08
• Description: 1:8 Clock Fanout Buffer
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Configuration
Pin Description
Document #: 38-07588 Rev. *A
1, 9,12,18,19,20,38 GND
2,8,13,29,17
3,4,5,6,14,15,16
10,11
37, 36,35,34,
33,32,31, 30,
28,27,26,25,
24,23,22,21
7
Pin Number
VDD
EN(1:7)
Input A, Input B
Q1(A,B), Q2(A,B)
Q3(A,B), Q4(A,B)
Q5(A,B), Q6(A,B)
Q7(A,B), Q8(A,B)
InConfig
Pin Name
POWER
POWER
LVTTL/LVCMOS
Default: LVPECL/LDVS
Optional: LVTTL/LVCMOS
single pin
LVPECL
LVTTL/LVCMOS
INPUT A
INPUT B
InConfig
Figure 1. Pin Diagram - 38-Pin TSSOP
Pin Standard Interface
GND
GND
GND
GND
VDD
GND
VDD
VDD
EN4
VDD
EN1
EN2
EN3
EN5
EN6
EN7
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Ground.
Power supply.
The respective outputs are enabled when these
pins are pulled high. Outputs are disabled when
connected to GND. EN7 controls both Q7(A,B) and
Q8(A,B)
Differential input pair or single line. LVPECL/LVDS
default. See InConfig, below.
Differential outputs.
Converts inputs from the default
LVPECL/LVDS (logic = 0)
to LVTTL/LVCMOS (logic = 1)
See
LVTTL/LVCMOS
additional information
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
Input Receiver Configuration for Differential or
Q3B
Q4B
Q5A
Q8A
GND
Q1A
Q1B
Q2A
Q2B
Q3A
Q4A
VDD
Q5B
Q6A
Q6B
Q7A
Q7B
Q8B
GND
table,
Description
Figure 6
and
Figure 7
CY2DP818-2
for
Page 2 of 9
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