CY2SSTV857 CYPRESS [Cypress Semiconductor], CY2SSTV857 Datasheet
CY2SSTV857
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CY2SSTV857 Summary of contents
Page 1
... In addition, the CY2SSTV857-27 features differential feedback clock outputs and inputs. This allows the CY2SSTV857- used as a zero-delay buffer. When used as a zero-delay buffer in nested clock trees, the CY2SSTV857-27 locks onto the input reference and translates with near-zero delay to low-skew outputs ...
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... For these applica- tions the CY2SSTV857-27 offers a differential clock input pair as a PLL reference. The CY2SSTV857-27 then can lock onto the reference and translate with near-zero delay to low-skew outputs. For normal operation, the external feedback input, FBIN, is connected to the feedback output, FBOUT ...
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... < 10 MHz Hi-Z Hi-Z t (phase error) t sk(o) t sk(o) Figure 1. Phase Error and Skew Waveforms t pd Figure 2. Propagation Delay Time t CY2SSTV857-27 FBOUT FBOUT# PLL L H BYPASSED/OFF H L BYPASSED/OFF Z Z Off Z Z OFF Hi-Z HI-Z Off , t PLH PHL ...
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... PLL 120 Ohm FBIN 120 Ohm FBIN# FBOUT FBOUT# Figure 4. Clock Structure # 1 = 2.5" PLL FBIN FBIN# FBOUT FBOUT# Figure 5. Clock Structure # 1 CY2SSTV857-27 t C(n+1) = 0.6" (Split to Terminator) DDR - SDRAM VTR 120 Ohm VCP DDR - SDRAM 0.3" = 0.6" (Split to Terminator) DDR-SDRAM DDR-SDRAM Stack DDR-SDRAM ...
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... Figure 6. Differential Signal Using Direct Termination Resistor Document #: 38-07464 Rev CY2SSTV857- Page ...
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... DD DDQ A Condition DDQ 60 MHz to 100 MHz 101 MHz to 170 MHz 20%–80% of VOD (all outputs) and is the voltage at which the differential signal must be crossing. DDQ CY2SSTV857-27 and V should be constrained to the in out < out DDQ DDQ [3] Min ...
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... TSSOP–Tape and Reel Lead-free CY2SSTV857ZXC-27 48-pin TSSOP CY2SSTV857ZXC-27T 48-pin TSSOP–Tape and Reel CY2SSTV857ZXI-27 48-pin TSSOP CY2SSTV857ZXI-27T 48-pin TSSOP–Tape and Reel Notes: 13. Period jitter and half-period jitter specifications are separate specifications that must be met independently of each other. 14. All differential input and output terminals are terminated with 120Ω/16 pF, as shown in Figure 5. ...
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... GAUGE PLANE MAX. 0.25[0.010] 0.20[0.008] 0.051[0.002] 0.152[0.006] 0.170[0.006] SEATING 0.279[0.011] PLANE CY2SSTV857-27 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.33gms PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG. 0.508[0.020] 0.762[0.030] 0°-8° ...
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... RGL Changed PD to PD# Removed the “and DDR266/PC2100” from the title Changed the part number from “CY2SSTV857” to “CY2SSTV857-27” Changed “Commercial Temp of 0°C to 70°C” to “Industrial Temp of –40° to +85°C” Added Industrial Temp part numbers to Ordering information ...