74ABT16240ADGG,112 NXP Semiconductors, 74ABT16240ADGG,112 Datasheet

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74ABT16240ADGG,112

Manufacturer Part Number
74ABT16240ADGG,112
Description
IC BUFF DVR TRI-ST 16BIT 48TSSOP
Manufacturer
NXP Semiconductors
Series
74ABTr
Datasheet

Specifications of 74ABT16240ADGG,112

Logic Type
Inverter
Number Of Inputs
4
Number Of Circuits
4
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935212210112
1. General description
2. Features and benefits
3. Ordering information
Table 1.
Type number
74ABT16240ADGG
74ABT16240ADL
Ordering information
Package
Temperature range Name
−40 °C to +85 °C
−40 °C to +85 °C
The 74ABT16240A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT16240A is an inverting 16-bit buffer that is ideal for driving bus lines. The
device features four output enable inputs (1OE, 2OE, 3OE, 4OE), each controlling four of
the 3-state outputs.
74ABT16240A
16-bit inverting buffer/line driver; 3-state
Rev. 05 — 25 May 2010
16-bit bus interface
Multiple V
Power-up 3-state
3-state buffers
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Output capability: +64 mA and −32 mA
Live insertion and extraction permitted
Latch-up protection exceeds 500 mA per JESD78 class II level A
ESD protection:
HBM JESD-A114E exceeds 2000 V
CDM JESD22-C101-C exceeds 1000 V
CC
and GND pins minimize switching noise
TSSOP48
SSOP48
Description
plastic thin shrink small outline package; 48 leads;
body width 6.1 mm
plastic shrink small outline package; 48 leads; body
width 7.5 mm
Product data sheet
Version
SOT362-1
SOT370-1

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74ABT16240ADGG,112 Summary of contents

Page 1

Rev. 05 — 25 May 2010 1. General description The 74ABT16240A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16240A is an inverting 16-bit ...

Page 2

... NXP Semiconductors 4. Functional diagram 1A0 1Y0 47 2 1A1 1Y1 46 3 1A2 1Y2 44 5 1A3 1Y3 43 6 1OE 1 2A0 2Y0 41 8 2A1 2Y1 40 9 2A2 2Y2 38 11 2A3 2Y3 37 12 2OE 48 Fig 1. Logic symbol 74ABT16240A Product data sheet 3A0 3Y0 36 13 3A1 ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 3. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin 1OE, 2OE, 3OE, 4OE 1, 48, 25, 24 1Y0, 1Y1, 1Y2, 1Y3 GND 4, 10, 15, 21, 28, 34, 39 18, 31 2Y0, 2Y1, 2Y2, 2Y3 8, 9, 11, 12 3Y0, 3Y1, 3Y2, 3Y3 ...

Page 4

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Control nOE [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage ...

Page 5

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Symbol Parameter V input clamping voltage HIGH-level output OH voltage V LOW-level output OL voltage I input leakage current I I power-off leakage OFF current I power-up/power-down O(pu/pd) output current I OFF-state output OZ current I output leakage current HIGH-state output current O I supply current CC Δ ...

Page 6

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V. For test circuit, see Figure Symbol Parameter Conditions t LOW to HIGH nAn to nYn, see PLH propagation delay t HIGH to LOW nAn to nYn, see PHL propagation delay t OFF-state to HIGH nOE to nYn; see PZH propagation delay ...

Page 7

... NXP Semiconductors 11. Waveforms input nAn output nYn and V are typical voltage output levels that occur with the output load Fig 4. Input (nAn) to output (nYn) propagation delay nOE input nYn output nYn output and V are typical voltage output levels that occur with the output load. ...

Page 8

... NXP Semiconductors 12. Test information Input pulse definition Test data is given in Table Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test circuit for 3-state outputs Fig 6. Load circuitry for switching times Table 8 ...

Page 9

... NXP Semiconductors 13. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 10

... NXP Semiconductors SSOP48: plastic shrink small outline package; 48 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT370-1 Fig 8 ...

Page 11

... Modifications: Table 74ABT16240A_4 20090325 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 74ABT16240A_3 20040212 74ABT_H16240A_2 19980225 74ABT_H16240A 19961001 ...

Page 12

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 13

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74ABT16240A Product data sheet 16 ...

Page 14

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Package outline ...

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