v54c333322v ETC-unknow, v54c333322v Datasheet - Page 4

• Manufacturer Part Number: v54c333322v
• Description: 200/183/166 Volt Ultra High Performance Sdram Banks 512kbit
• Manufacturer: ETC-unknow

MOSEL VITELIC
Signal Pin Description
V54C333322V Rev. 2.0 May 2000
Pin
CLK
CKE
CS
CAS
WE
A
BA
DQ
DQMi
VDD/VSS
VDDQ/VSSQ
RAS
NC
0
-A
0
-DQ
10
31
Name
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address
Bank Select
Data Input/Output
Data Input/Output Mask
Power Supply/Ground
Data Output Power/Ground
No Connection
Input Function
System clock input. Active on the positive rising edge to sample all inputs
Activates the CLK signal when high and deactivates the CLK when low.
CKE low initiates the power down mode, suspend mode, or the self re-
fresh mode
Disables or enables device operation by masking or enabling all inputs
except CLK, CKE and DQMi
Latches row addresses on the positive edge of CLK with RAS low. En-
ables row access & precharge
Latches column addresses on the positive edge of CLK with CAS low.
Enables column access
Enables write operation
During a bank activate command, A
During a read or write command, A
addition to the column address A
define the bank to be precharged. A
during a precharge cycle, If A
A
Selects which bank to activate. BA low select bank A and high selects
bank B
Data inputs/output are multiplexed on the same pins
Makes data output Hi-Z. Blocks data input when DQM is active
Power Supply. +3.3V
Provides isolated power/ground to DQs for improved noise immunity
8
is low, the BA is used to decide which bank to precharge
4
0.3V/ground
8
is high, both bank will be precharged, if
8
is used to invoke auto precharge BA
0
0
8
-A
-A
is low, auto precharge is disabled
7
10
defines the column address. In
defines the row address.
V54C333322V