v54c333322v ETC-unknow, v54c333322v Datasheet - Page 6

• Manufacturer Part Number: v54c333322v
• Description: 200/183/166 Volt Ultra High Performance Sdram Banks 512kbit
• Manufacturer: ETC-unknow

Burst Length and Sequence:
MOSEL VITELIC
Read and Write Operation
at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the select-
ed bank is activated and all of sense amplifiers as-
sociated to the wordline are set. A CAS cycle is
triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, t
RAS timing. WE is used to define either a read
(WE = H) or a write (WE = L) at this stage.
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 166 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set opera-
tion, i.e., one of 1, 2, 4, 8 and full page. Column ad-
dresses are segmented by the burst length and
serial data accesses are done within this boundary.
The first column address to be accessed is supplied
at the CAS timing and the subsequent addresses
are generated automatically by the programmed
burst length and its sequence. For example, in a
burst length of 8 with interleave sequence, if the first
address is ‘2’, then the rest of the burst sequence is
3, 0, 1, 6, 7, 4, and 5.
the sequential burst type and page length is a func-
tion of the I/O organisation and column addressing.
Full page burst operation do not self terminate once
the burst length has been reached. In other words,
unlike burst length of 2, 3 or 8, full page burst con-
tinues until it is terminated using another command.
V54C333322V Rev. 2.0 May 2000
Length
Burst
Page
When RAS is low and both CAS and WE are high
SDRAM provides a wide variety of fast access
Full page burst operation is only possible using
Full
2
4
8
Starting Address
(A2 A1 A0)
000
001
010
011
100
101
110
111
xx0
xx1
x01
x10
x11
x00
nnn
Sequential Burst Addressing
0
1
2
3
4
5
6
7
Cn, Cn+1, Cn+2,.....
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
(decimal)
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
RCD
0, 1
1, 0
3
4
5
6
7
0
1
2
, from the
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
DRAM’s, burst read or write accesses on any col-
umn address are possible once the RAS cycle
latches the sense amplifiers. The maximum t
the refresh interval time limits the number of random
column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining ad-
dresses are overridden by the new address with the
full burst length. An interrupt which accompanies
with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
sequentially, interleaved bank read or write
operations are possible. With the programmed
burst length, alternate access and precharge
operations on two or more banks can realize fast
serial data access modes among many different
pages. Once two or more banks are activated,
column to column interleave operation can be done
between different pages.
Refresh Mode
and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any re-
fresh mode. An on-chip address counter increments
the word and the bank addresses and no bank infor-
mation is required for both refresh modes.
Similar to the page mode of conventional
When two or more
SDRAM has two refresh modes, Auto Refresh
Interleave Burst Addressing
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
(decimal)
not supported
2
3
0
1
6
7
4
5
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
3
2
1
0
7
6
5
4
0, 1
1, 0
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
banks are activated
7
6
5
4
3
2
1
0
V54C333322V
RAS
or