FS6377-01 American Microsystems, Inc., FS6377-01 Datasheet - Page 22

• Manufacturer Part Number: FS6377-01
• Description: Programmable 3-pll Clock Generator ic
• Manufacturer: American Microsystems, Inc.

FS6377-01
FS6377-01
Programmable 3-PLL Clock Generator IC
Programmable 3-PLL Clock Generator IC
11.4.1 Example Programming
Type a value for the crystal resonator frequency in MHz
in the Reference Crystal box. This frequency provides
the basis for all of the PLL calculations that follow.
Next, click on the PLL A box. A pop-up screen similar to
Figure 15 should appear. Type in a desired Output Clock
frequency in MHz, set the operating voltage (3.3V or 5V),
and the desired maximum output frequency error. Press-
ing Calculate Solutions generates several possible di-
vider and VCO-speed combinations.
Figure 15: PLL Screen
For a 100MHz output, the VCO should ideally operate at
a higher frequency, and the Reference and Feedback
Dividers should be as small as possible. In this example,
highlight Solution #7. Notice the VCO operates at
200MHz with a Post Divider of 2 to obtain an optimal 50%
duty cycle.
Now choose which Mux and Post Divider to use (that is,
choose an output pin for the 100MHz output). Selecting A
places the PostDiv value in Solution #7 into Post Divider
A and switches Mux A to take the output of PLL A.
The PLL screen should disappear, and now the value in
the PLL A box is the new VCO frequency chosen in Solu-
tion #7. Also note that Mux A has been switched to PLL A
and the Post Divider A has the chosen 100MHz output
displayed.
Repeat the steps for PLL B.
FS6377-01
FS6377-01
Programmable 3-PLL Clock Generator IC
Programmable 3-PLL Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
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PLL C supports two different output frequencies depend-
ing on the setting of the SEL_CD pin. Both Mux C and
Mux D are also affected by the logic level on the SEL_CD
pin, as are the Post Dividers C and D.
Figure 16: Post Divider Menu
information can be downloaded out the PC parallel port to
the FS6377 (not available on Windows NT).
The register settings are shown to the left in the screen
shown in Figure 14. Clicking on a register location dis-
plays a screen shown in Figure 17. Individual bits can be
poked, or the entire register value can be changed.
Figure 17: Register Screen
Click on PLL C1 to open the PLL
screen. Set a desired frequency,
however, now choose the Post
Divider B as the output divider.
Notice the Post Divider box has split
in two (as shown in Figure 16). The
Post Divider B box now shows that
the divider is dependent on the
setting of the SEL_CD pin for as
long as Mux B is the PLL C output.
Clicking on Post Divider A reveals a
pull-down menu provided to permit
adjustment of the Post Divider value
independently of the PLL screen. A
typical menu is shown in Figure 16.
The range of possible post divider
values is also given in Table 8.
Once all of the PLLs, switches, and
post dividers have been set, the
11.22.02