FS6377-01 American Microsystems, Inc., FS6377-01 Datasheet - Page 4

• Manufacturer Part Number: FS6377-01
• Description: Programmable 3-pll Clock Generator ic
• Manufacturer: American Microsystems, Inc.

FS6377-01
FS6377-01
Programmable 3-PLL Clock Generator IC
Programmable 3-PLL Clock Generator IC
4.2
As shown in Figure 2, an input mux in front of each Post
Divider stage can select from any one of the PLL fre-
quencies or the reference frequency. The frequency se-
lection is done via the I
The input frequency on two of the four muxes (Mux C and
D in Figure 2) can be changed without reprogramming by
a logic-level input on the SEL_CD pin.
4.3
The Post Divider performs several useful functions. First,
it allows the VCO to be operated in a narrower range of
speeds compared to the variety of output clock speeds
that the device is required to generate. Second, it
changes the basic PLL equation to
where N
Post Divider moduli respectively, and f
output and reference oscillator frequencies. The extra
integer in the denominator permits more flexibility in the
programming of the loop for many applications where
frequencies must be achieved exactly.
The modulus on two of the four Post Dividers muxes
(Post Dividers C and D in Figure 2) can be altered with-
out reprogramming by a logic level on the SEL_CD pin.
5.0
The FS6377 powers up with all internal registers cleared
to zero, delivering the crystal frequency to all outputs. For
operation to occur, the registers must be loaded in a
most-significant-bit (MSB) to least-significant-bit (LSB)
order. The register mapping of the FS6377 is shown in
Table 3, and I
in Section 6.0.
Control of the Reference, Feedback, and Post Dividers is
detailed in Table 6. Selection of these dividers directly
controls how fast the VCO will run. The maximum VCO
speed is noted in Table 15.
FS6377-01
FS6377-01
Programmable 3-PLL Clock Generator IC
Programmable 3-PLL Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
Post Divider Muxes
Post Dividers
Device Operation
F
, N
R
, and N
2
C-bus programming information is detailed
f
CLK
P
are the Feedback, Reference, and
2
C-bus.
f
REF
æ
ç ç
è
N
N
F
R
ö
÷ ÷
ø
æ
ç ç
è
N
1
CLK
P
ö
÷ ÷
ø
and f
REF
are the
4
5.1
The SEL_CD pin provides a way to alter the operation of
PLL C, Muxes C and D, and Post Dividers C and D with-
out having to reprogram the device. A logic-low on the
SEL_CD pin selects the control bits with a “C1” or “D1”
notation, per Table 3. A logic-high on the SEL_CD pin
selects the control bits with “C2” or “D2” notation, per
Table 3.
Note that changing between two running frequencies us-
ing the SEL_CD pin may produce glitches in the output,
especially if the post-divider(s) is/are altered.
5.2
A logic-high on the PD pin powers down only those por-
tions of the FS6377 which have their respective power-
down control bits enabled. Note that the PD pin has an
internal pull-up.
When a Post Divider is powered down, the associated
output driver is forced low. When all PLLs and Post Di-
viders are powered down the crystal oscillator is also
powered down. The XIN pin is forced low, and the XOUT
pin is pulled high.
A logic-low on the OE pin tristates all output clocks. Note
that this pin has an internal pull-up.
5.3
For applications where an external reference clock is
provided (and the crystal oscillator is not required), the
reference clock should be connected to XOUT and XIN
should be left unconnected (float).
For best results, make sure the reference clock signal is
as jitter-free as possible, can drive a 40pF load with fast
rise and fall times, and can swing rail-to-rail.
If the reference clock is not a rail-to-rail signal, the refer-
ence must be AC coupled to XOUT through a 0.01µF or
0.1µF capacitor. A minimum 1V peak-to-peak signal is
required to drive the internal differential oscillator buffer.
SEL_CD Input
Power-Down and Output Enable
Oscillator Overdrive
11.22.02