em3027 EM Microelectronic, em3027 Datasheet - Page 18

• Manufacturer Part Number: em3027
• Description: Real-time Clock With I2c Or Spi Interface, Crystal Temperature Compensation, Battery Switchover And Trickle Charger
• Manufacturer: EM Microelectronic

8.9
The purpose of EEBusy bit is to inform users about current status of the EEPROM operations.
EEBusy – status of EEPROM controller (if EEBusy = ‘1’ then Configuration Registers refresh or EEPROM write in progress)
The purpose of the following status bits is to record status of power supply voltage and Self-Recovery system/System reset
behaviour.
If one of these status bits is set, it can be cleared only by writing ‘0’, there is no automatic reset if the set condition
disappears.
8.10
There are five interrupt sources which can output an interrupt on (INT and/or IRQ/CLKOUT) pins. The request
is generated when at least one of IRQflags goes to ‘1’ (OR function).
Each interrupt source has its own interrupt enable (AIntE, TIntE, V1IntE, V2IntE, SRIntE). When the interrupt enable is ‘1’
then the appropriate interrupt source is enabled.
Interrupt flags (IRQflags) are cleared by ‘0’ writing into the appropriate bit. In case of V1F, V2F and SRF bits, it is necessary
to clear also corresponding status bits (Status) after interrupt bit.
8.11
The purpose of the Self-Recovery System (SRS) is to generate an internal chip reset in case the on chip state machine
goes into a deadlock. The function is based on an internal counter that is periodically reset by the control logic. If it is not
reset properly on time, the chip reset will take place. It is executed after two voltage monitoring periods at the latest, i.e. 2s
or 32s (ThPer bit).
A possible source of a deadlock could be polluted electrical environment (EMC problem, disturbed power supply, etc.).
SRS sets status bit SR and resets the whole internal logic except Watch, Alarm and Timer parts (i.e. time information are
not affected). Furthermore, if the SRS interrupt is enabled (SRIntE='1'), the SRF flag is set after the internal chip reset.
Note, that SROn='1' and SRIntE='0' after the reset.
After the internal chip reset, the device starts with the power-up sequence (see chapter 8).
SRS is automatically enabled after power-up (SROn bit). It can be disabled by writing '0' into the SROn.
8.12
The address range of the EM3027 is divided into pages. The page is addressed by the five most significant bits of the
address. The three low significant bits of the address provide selection of registers inside the page. During address
incrementing only three low significant bits are changed. The page address part is fixed during whole data transmission.
8.13
The 32.768 kHz Xtal oscillator and the clock divider provide the timing signal for the functional blocks. Prescaler block is
responsible for frequency division of the 32.768 kHz clock signal coming from the Xtal oscillator. Divided frequency is then
distributed between other blocks inside the chip including Watch, Timer and control logic.
Two capacitors C
Copyright © 2008, EM Microelectronic-Marin SA
07/08 – rev B
Status Register
Interrupts
Self-Recovery System
Register Map
Xtal Oscillator and Prescaler
PON
VLOW1 – status of Vlow1 voltage detection
VLOW2 – status of Vlow2 voltage detection
SR
AF
TF
V1F
V2F
SRF
R
IN
– status of Power-ON
– status of the Self-Recovery system/System reset
– interrupt is provided when Watch time reaches Alarm time settings and comparison is enabled
– interrupt is provided when Timer reaches ZERO
– interrupt is provided when supply voltage is below Vlow1 (VLOW1 status “rising edge”)
– interrupt is provided when supply voltage is below Vlow2 (VLOW2 status “rising edge”)
– interrupt is provided when Self-Recovery system invoked internal reset (SR status “rising edge”)
and C
OUT
are integrated on chip – see Figure 5.
18
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