k9k8g08u0m-y Samsung Semiconductor, Inc., k9k8g08u0m-y Datasheet - Page 39

Manufacturer Part Number

k9k8g08u0m-y

Description

1g X 8 Bit / 2g X 8 Bit Nand Flash Memory

Manufacturer

Samsung Semiconductor, Inc.

Datasheet

1.K9K8G08U0M-Y.pdf (49 pages)

Device Operation

PAGE READ

Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command

is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data

within the selected page are transferred to the data registers in less than 20 s(t

this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read

out in 25ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the

data starting from the selected column address up to the last column address.

The device may output random data in a page instead of the consecutive sequential data by writing random data output command.

The column address of next data, which is going to be out, may be changed to the address which follows random data output com-

mand. Random data output can be operated multiple times regardless of how many times it is done in a page.

Figure 6. Read Operation

I/Ox

CLE

ALE

R/B

K9WAG08U1M

K9K8G08U0M

00h

x x x x

Col. Add.1,2 & Row Add.1,2,3

x x x x

Address(5Cycle)

x x x

30h

Data Field

x x x x x x x x x x x x x x x x x x x

Spare Field

). The system controller can detect the completion of

Data Output(Serial Access)

FLASH MEMORY

Preliminary