CS42426_05 CIRRUS [Cirrus Logic], CS42426_05 Datasheet - Page 13
![no-image](/images/no-image-200.jpg)
CS42426_05
Manufacturer Part Number
CS42426_05
Description
114 dB, 192 kHz 6-Ch Codec with PLL
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
1.CS42426_05.pdf
(73 pages)
- Current page: 13 of 73
- Download datasheet (2Mb)
DS604F1
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI
(For CQZ, T
Inputs: Logic 0 = DGND, Logic 1 = VLC, C
Notes:
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
20. Data must be held for sufficient time to bridge the transition time of CCLK.
21. For f
A
= -10 to +70° C; For DQZ, T
sck
<1 MHz.
Parameter
CDOUT
CDIN
CCLK
CS
t css
Figure 4. Control Port Timing - SPI Format
t r2
A
L
= -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V;
= 30 pF)
t dsu
t scl
t f2
(Note 20)
(Note 21)
(Note 21)
t sch
t dh
t pd
Symbol
f
t
t
t
t
t
t
t
csh
sch
dsu
t
t
t
t
sck
css
scl
dh
pd
r1
f1
r2
f2
Min
1.0
20
66
66
40
15
0
-
-
-
-
-
t csh
™
Typ
FORMAT
-
-
-
-
-
-
-
-
-
-
-
-
Max
100
100
6.0
50
25
25
-
-
-
-
-
-
CS42426
Units
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
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