CS42426_05 CIRRUS [Cirrus Logic], CS42426_05 Datasheet - Page 5
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CS42426_05
Manufacturer Part Number
CS42426_05
Description
114 dB, 192 kHz 6-Ch Codec with PLL
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
1.CS42426_05.pdf
(73 pages)
- Current page: 5 of 73
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CS42426
LIST OF TABLES
Table 1. Common OMCK Clock Frequencies ............................................................................................ 24
Table 2. Common PLL Output Clock Frequencies..................................................................................... 24
Table 3. Slave Mode Clock Ratios ............................................................................................................. 25
Table 4. Serial Audio Port Channel Allocations ......................................................................................... 26
Table 5. DAC De-Emphasis ....................................................................................................................... 44
Table 6. Digital Interface Formats .............................................................................................................. 45
Table 7. ADC One-Line Mode.................................................................................................................... 45
Table 8. DAC One-Line Mode.................................................................................................................... 45
Table 9. RMCK Divider Settings ................................................................................................................ 48
Table 10. OMCK Frequency Settings ........................................................................................................ 48
Table 11. Master Clock Source Select....................................................................................................... 49
Table 12. PLL Clock Frequency Detection................................................................................................. 50
Table 13. Example Digital Volume Settings ............................................................................................... 53
Table 14. ATAPI Decode ........................................................................................................................... 54
Table 15. Example ADC Input Gain Settings ............................................................................................. 55
Table 16. PLL External Component Values ............................................................................................... 62
DS604F1
5
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