CS4341A-KS CIRRUS [Cirrus Logic], CS4341A-KS Datasheet - Page 28

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CS4341A-KS

Manufacturer Part Number
CS4341A-KS
Description
24-Bit, 192 kHz Stereo DAC with Volume Control?
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet

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SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE
Notes: 6. t
28
SPI Mode
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
7. Data must be held for sufficient time to bridge the transition time of CCLK.
8. For f
spi
only needed before first falling edge of CS after RST rising edge. t
sclk
< 1 MHz.
C C LK
C D IN
R S T
C S
Parameter
t srs
t spi
Figure 21. Control Port Timing - SPI Mode
t r2
t css
t scl
t f2
t dsu t dh
(Note 6)
(Note 7)
(Note 8)
(Note 8)
t sch
Symbol
f
t
t
t
t
t
t
t
t
sclk
dsu
t
csh
css
sch
t
srs
spi
scl
dh
r2
f2
Min
500
500
1.0
20
66
66
40
15
-
-
-
t csh
spi
= 0 at all other times.
(Continued)
Max
100
100
6
-
-
-
-
-
-
-
-
CS4341A
DS582PP1
MHz
Unit
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns

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