CS47014-CVZR CIRRUS [Cirrus Logic], CS47014-CVZR Datasheet - Page 23

• Manufacturer Part Number: CS47014-CVZR
• Description: High Definition Audio Decoder DSP Family with Dual 32-bit DSP Engine Technology
• Manufacturer: CIRRUS [Cirrus Logic]

5.18 Switching Characteristics — Digital Audio Output Port
DS752PP8
DAO_MCLK period
DAO_MCLK duty cycle
DAO_SCLK period for Master or Slave mode
DAO_SCLK duty cycle for Master or Slave mode
DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input
DAO_SCLK delay from DAO_LRCLK transition, respectively
DAO_LRCLK delay from DAO_SCLK transition, respectively
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition
DAO_LRCLK delay from DAO_SCLK transition, respectively
DAO_SCLK delay from DAO_LRCLK transition, respectively
1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS4970x4 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is
3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the
4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
DAOn_DATAn
DAO_SCLK
divided to produce DAO_SCLK, DAO_LRCLK.
point at which the data is valid.
DAO_LRCLK
DAO_MCLK
Master Mode (Output A1 Mode)
Slave Mode (Output A0 Mode)
t
daomdv
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
Parameter
Figure 13. Digital Audio Port Output Timing Master Mode
3
3
t
daomlclk
t
daomsck
1
t
1
Copyright 2009 Cirrus Logic
daomlrts
1,2
4
3
3
3
3
DAOn_DATAn
DAO_SCLK
DAO_LRCLK
DAO_MCLK
Symbol
T
t
T
t
t
t
t
t
daomsck
daomlrts
daomstlr
t
daomdv
daomclk
daosstlr
daoslrts
daosdv
daosclk
32-bit High Definition Audio Decoder DSP Family
-
-
Min
40
45
40
40
-
-
-
-
-
-
-
t
daomstlr
t
daomclk
t
daomsck
Max
CS4970x4 Data Sheet
55
60
19
10
15
30
15
8
8
-
-
Unit
ns
%
ns
%
ns
ns
ns
ns
ns
ns
ns
23