SN74LS161D ONSEMI [ON Semiconductor], SN74LS161D Datasheet - Page 5

• Manufacturer Part Number: SN74LS161D
• Description: BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS
• Manufacturer: ONSEMI [ON Semiconductor]

AC SETUP REQUIREMENTS
*CEP, CET or DATA
DEFINITION OF TERMS
SETUP TIME (t s ) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW to HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (t h ) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued recog-
t W CP
t W
t s
t s
t h
t h
t rec
CP
Q
S
Symbol
Figure 1. Clock to Output Delays, Count
b l
Frequency, and Clock Pulse Width
1.3 V
t W (H)
Clock Pulse Width Low
MR or SR Pulse Width
Setup Time, other*
Setup Time PE or SR
Hold Time, data
Hold Time, other
Recovery Time MR to CP
t PHL
1.3 V
t W (L)
P
Parameter
(T A = 25 C)
1.3 V
SN54/74LS160A SN54/74LS161A
SN54/74LS162A SN54/74LS163A
t PLH
1.3 V
OTHER CONDITIONS:
PE = MR (SR) = H
CEP = CET = H
FAST AND LS TTL DATA
Min
25
20
20
25
15
3
0
AC WAVEFORMS
Limits
Typ
5-5
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW to
HIGH and still be recognized.
RECOVERY TIME (t rec ) — is defined as the minimum time re-
quired between the end of the reset pulse and the clock transi-
tion from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
Figure 2. Master Reset to Output Delay, Master Reset
Max
Q 0 Q 1 Q 2 Q 3
MR
CP
Pulse Width, and Master Reset Recovery Time
1.3 V
U i
Unit
ns
ns
ns
ns
ns
ns
ns
t W
t PHL
t rec
T
Test Conditions
1.3 V
V
V
V
V CC = 5.0 V
1.3 V
C
di i
5 0 V
5 0 V
5 0 V
OTHER CONDITIONS:
PE = L
P 0 = P 1 = P 2 = P 3 = H