W164 Cypress Semiconductor Corp., W164 Datasheet
W164
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W164 Summary of contents
Page 1
... CPU1 GND VDDQ3 PCI_F PCI1 PCI2 PCI3 PCI4 PCI5 PCI6 GND VDDQ3 48MHz 24/48MHz GND • 3901 North First Street • San Jose W164 Frequency Generator = 3.3V±5% DDQ3 V = 2.5V±5% DDQ2 1 V/ns pull-up CPU(0:1) PCI 100 MHz 33.3 MHz 66.8 MHz 33.4 MHz 1 28 GND 2 27 ...
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... DD Figure 2 show two suggested methods for strapping resistor connections. Upon W164 power-up, the first operation is used for input logic selection. During this period, the Reference clock output buffer is three-stated, allowing the output strapping re- sistor on the l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic “ ...
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... Table 2 summarizes the control functions of the serial data interface. Operation Data is written to the W164 in ten bytes of eight bits each. Bytes are written in the order shown in Table 3. Common Application Unused outputs are disabled to reduce EMI and system power ...
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... Data Byte 6 Byte Description Commands the W164 to accept the bits in Data Bytes 3–6 for internal register configuration. Since other devices may exist on the same com- mon serial data bus necessary to have a specific slave address for each potential receiver. The slave receiver address for the W164 is 11010010 ...
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... Default -- Refer to Table 5 Refer to Table 5 Refer to Table 5 Frequency Controlled by BYT3 SEL_(3:0) Table Active -- -- -- Active -- Active Active Active Active -- Active Active Active Active -- -- Active -- -- -- Active 1 Active 1 W164 [1] [1] ...
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... Output Conditions Bit 0 CPU0:1 PCI_F, PCI1:6 0 Note 2 Note 2 1 X1/2 CPU/ ±0.5% ±0.5% 1 Hi-Z Hi-Z 6 W164 If Spread Is On PCI Clocks (MHz) Spread Percentage 34.25 ±0.5% Center 37.5 ±0.5% Center 41.6 ±0.5% Center 33.4 ±0.5% Center 34.25 ±0.5% Center 37.3 ±0.5% Center 33.3 ±0.5% Center 33.3 ±0.5% Center 39.0 ± ...
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... All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section. 4. W164 logic inputs have internal pull-up resistors, except SEL100/66# (pull-ups not full CMOS level). above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability ...
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... DD 6. The W164 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). ...
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... Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 9 W164 CPU = 66.8/100 MHz Min. Typ. Max. Unit 30 ns ...
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... Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to fre- quency stabilization. Average value during switching transition. Used for determining series termination value. Package Type 28-pin SOIC (300 mils) 10 W164 CPU = 66.8/100 MHz Min. Typ. Max. Unit 48.008 MHz 24 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W164 ...