cx25870 Conexant Systems, Inc., cx25870 Datasheet - Page 121

• Manufacturer Part Number: cx25870
• Description: Video Encoder With Adaptive Flicker Filtering And Hdtv Output
• Manufacturer: Conexant Systems, Inc.

CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (7 of 16)
100381B
DIS_GMUSHY
DIS_PLL
DIS_SCRST
DIS_YLPF
DIV2
DIV2_LATCH
DR_LIMITN[10:8}
DR_LIMITN[7:0]
DR_LIMITP[10:8}
DR_LIMITP[7:0]
DRVS[1:0]
E656
EACTIVE
EBLUE
ECBAR
ECCF1(ECC)
ECCF2(EXDS)
Bit/Register
Names
Bit 6–D4 and
Bit 0–3A
Bit 6–D6
Bit 2–6C
Bit 7–CA
Bit 2–30
Bit 4–A2
Bit 7–C8
bit 4–38
Bits [5:3]–4E and
bits [7:0]–4C
Bits [2:0]–4E and
bits [7:0]–4A
Bits [6:5]–32
Bit 4–D6
Bit 2–C4
Bit 4–C4
Bit 5–C4
Bit Location
0 = Enables Luma Anti-Pseudo Gamma Removal.
1 = Disables Luma Anti-Pseudo Gamma Removal. (DEFAULT)
0 = PLL enable. (DEFAULT)
1 = PLL disable.
In nonsleep mode, if an external clock is being used and the PLL is not needed, this bit
will disable the PLL function.
NOTE(S):
0 = Normal operation. The subcarrier phase is reset to 0 at the beginning of each color
field sequence. (DEFAULT)
1 = Disables subcarrier reset event at beginning of field sequence.
0 = Enable Luma Initial Horizontal Low Pass filter. (DEFAULT)
1 = Disable Luma Initial Horizontal Low Pass filter.
0 = Normal operation. (DEFAULT)
1 = Divides input pixel rate by two (for CCIR601 interlaced timing input). Useful for DVD
playback resolutions. The DIV2 bit in register D4 was kept for Bt868/869 compatibility
purposes. The DIV2 bit in register 38 is autoconfigurable. These bit values always mirror
each other. Changing the state of one DIV2 register field automatically updates the other
DIV2 register field.
This bit only has an effect when DIV2 = 1.
0 = Data is clocked at rising edge of CLKI while encoder is in DIV2 mode. (DEFAULT)
1 = Data is clocked at rising and falling edges of CLKI.
Lower bound limit for DR frequency deviation in SECAM. Review SECAM Output
Section.
Upper bound limit for DR frequency deviation in SECAM. Review SECAM Output Section.
Controls the low voltage pad drive strength. Review Low Voltage Graphics Interface
section.
00 = 3.3 V peak-to-peak signal levels (DEFAULT)
01 = 1.8 V peak-to-peak signal levels
10 = 1.5 V and 1.3 V peak-to-peak signal levels
11 = 1.1 V peak-to-peak signal levels
0 = Input pixel format defined by IN_MODE[3:0] register. (DEFAULT)
1 = CCIR 656 input on P[7:0] port.
0 = Black burst.
1 = Enable normal video. (DEFAULT)
0 = Normal operation. (DEFAULT)
1 = Generate blue field.
0 = Normal operation. (DEFAULT)
1 = Enable standard color bars.
1 = Enables closed-caption encoding on field 1.
0 = Disables closed-caption encoding on field 2. (DEFAULT)
1 = Enables closed-caption encoding on field 2.
0 = Disables closed-caption encoding on field 1. (DEFAULT)
Some of the special modes are not available when the PLL is disabled.
Conexant
Bit/Register Definition
2.0 Internal Registers
2.4 Reading Registers
2-15