cx25870 Conexant Systems, Inc., cx25870 Datasheet - Page 35

• Manufacturer Part Number: cx25870
• Description: Video Encoder With Adaptive Flicker Filtering And Hdtv Output
• Manufacturer: Conexant Systems, Inc.

CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-6. Operating the CX25870/871 in Pseudo-Master Interface
100381B
1.3.7.3 Pseudo-Master
1.3.7.2 Reason for
Interface
BLANK*
Controller
Graphics
If the graphics controller possesses pixel-based resolution (i.e., pixels are only a
single pixel clock wide) then the encoder does not have to transmit or receive the
BLANK* signal. However, for graphics controllers that are character clock based,
a BLANK* signal is necessary.
pixel clocks in duration. This causes several pixel clocks to elapse, resulting in an
erroneous delay prior to the next HSYNC* being observed by the encoder and the
next line starting. The only method of compensating for this delay is for character
clock based controllers to use the BLANK* signal. This signal is required in the
physical interface to indicate the exact location of the first active pixel on each
line.
In pseudo-master interface, the CX25870/871 generates clock reference signal,
CLKO as an output. This signal’s purpose is to inform the graphics controller the
exact frequency at which the data must be sent to the encoder. Timing signals,
HSYNC*, VSYNC*, and BLANK*, are received by the encoder as inputs. The
leading edges of these signals denote when a new clock period, new line, and new
frame starts, respectively. Because this connection scheme shares mastering
responsibilities, the interface is also named clocking master/timing slave.
graphics controller as the timing master device.
data- P[7:0]) and 1 output (CLKO) are required for this configuration. The
amount of inputs could grow as high as 28 if 24-bit RGB nonmultiplexed mode is
chosen as the Input Pixel Mode (i.e., IN_MODE[3:0] = 0111) by the designer.
the encoder’s reference clock and send back a version of that clock at the same
frequency with the pixel data transitions synchronized to CLKI’s rising and
falling edges. This is accomplished via the VGA encoder’s clock output (CLKO)
and clock input (CLKI) ports.
The BLANK line is necessary because a character clock is actually 8 or 9
An illustration of the pseudo-master interface is illustrated below using the
A minimum of 11 inputs (CLKI, HSYNC*, VSYNC*, and 8 lines for pixel
Pseudo-Master interface can only exist if the graphics controller can accept
Delay
HSYNC*
VSYNC*
BLANK*
RGB or
YCrCb
Clock
Clock
Conexant
CLKI
CX25870/
CX25871
CLKO
Composite #1
Luma
Chroma
Composite #2
1.0 Functional Description
1.3 Device Description
100381_055
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