m5lv-128-104-10yi Lattice Semiconductor Corp., m5lv-128-104-10yi Datasheet - Page 24

• Manufacturer Part Number: m5lv-128-104-10yi
• Description: Mach 5 Cpld Family Fifth Generation Mach Architecture
• Manufacturer: Lattice Semiconductor Corp.

M5(LV) TIMING PARAMETERS OVER OPERATING RANGES
24
Power Delays:
t
t
t
Additional Cluster Delay:
t
Interconnect Delays:
t
t
Reset and Preset Delays:
t
t
t
t
Clock Enable Delays:
t
t
Width:
t
t
t
t
t
t
PL1
PL2
PL3
PT
BLK
SEG
SRi
SR
SRR
SRW
CES
CEH
WLS
WHS
WLA
WHA
GWA
WIR
Power level 1 delay (Note 2)
Power level 2 delay (Note 2)
Power level 3 delay (Note 2)
Product term cluster delay
Block interconnect delay
Segment interconnect delay
Asynchronous reset or preset to internal
register output
Asynchronous reset or preset to register
output
Reset and set register recovery time
Asynchronous reset or preset width
Clock enable setup time
Clock enable hold time
Global clock width low (Note 3)
Global clock width high (Note 3)
Product term clock width low
Product term clock width high
Gate width low (for low transparent) or
high (for high transparent)
Input register clock width low or high
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
5.5
3.0
4.0
3.0
2.5
2.5
3.0
3.0
3.0
3.0
-5
(5.0)
(9.0)
(17.5)
4.0
6.0
9.0
0.3
1.5
4.5
6.0
8.0
7.5
4.0
5.0
4.0
3.0
3.0
4.0
4.0
4.0
4.0
MACH 5 Family
-6
10.0
4.0
6.0
9.0
0.3
1.5
4.5
8.0
7.5
4.0
5.0
4.0
3.0
3.0
4.0
4.0
4.0
4.0
-7
(5.0)
(9.0)
(17.5)
10.0
4.0
6.0
9.0
0.3
1.5
5.0
8.0
8.0
5.0
6.0
5.0
4.0
4.0
5.0
5.0
5.0
5.0
-10
(5.0)
(9.0)
(17.5)
10.0
12.0
4.0
6.0
9.0
0.3
2.0
6.0
9.0
6.0
7.0
6.0
5.0
5.0
6.0
6.0
6.0
6.0
-12
(5.0)
(9.0)
(17.5)
12.0
14.0
1
4.0
6.0
9.0
0.3
2.0
6.0
(CONTINUED)
10.0
7.0
7.0
6.0
6.0
6.0
7.0
7.0
7.0
7.0
-15
(5.0)
(9.0)
(17.5)
14.0
16.0
4.0
6.0
9.0
0.3
2.0
6.0
11.0
8.0
8.0
7.0
6.0
6.0
8.0
8.0
8.0
8.0
-20
(5.0)
(9.0)
(17.5)
16.0
18.0
4.0
6.0
9.0
0.3
2.0
6.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns