h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 12

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h8s-2169

Manufacturer Part Number
h8s-2169
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
2.9
2.10 Usage Note........................................................................................................................ 77
Section 3 MCU Operating Modes
3.1
3.2
3.3
3.4
3.5
Section 4 Exception Handling
4.1
4.2
4.3
4.4
4.5
4.6
Rev. 3.00 Jan 18, 2006 page xii of xxviii
2.8.5
2.8.6
Basic Timing ..................................................................................................................... 72
2.9.1
2.9.2
2.9.3
2.9.4
2.9.5
2.10.1 TAS Instruction.................................................................................................... 77
2.10.2 STM/LDM Instruction ......................................................................................... 77
Overview........................................................................................................................... 79
3.1.1
3.1.2
Register Descriptions ........................................................................................................ 80
3.2.1
3.2.2
3.2.3
3.2.4
Operating Mode Descriptions ........................................................................................... 86
3.3.1
3.3.2
3.3.3
Pin Functions in Each Operating Mode ............................................................................ 87
Memory Map in Each Operating Mode ............................................................................ 87
Overview........................................................................................................................... 91
4.1.1
4.1.2
4.1.3
Reset.................................................................................................................................. 94
4.2.1
4.2.2
4.2.3
Interrupts ........................................................................................................................... 97
Trap Instruction................................................................................................................. 98
Stack Status after Exception Handling.............................................................................. 99
Notes on Use of the Stack ................................................................................................. 100
Bus-Released State............................................................................................... 71
Power-Down State ............................................................................................... 71
Overview.............................................................................................................. 72
On-Chip Memory (ROM, RAM) ......................................................................... 72
On-Chip Supporting Module Access Timing (Internal I/O Register 1 and 2) ..... 74
On-Chip Supporting Module Access Timing (Internal I/O Register 3) ............... 75
External Address Space Access Timing .............................................................. 77
Operating Mode Selection ................................................................................... 79
Register Configuration......................................................................................... 80
Mode Control Register (MDCR) ......................................................................... 80
System Control Register (SYSCR) ...................................................................... 81
Bus Control Register (BCR) ................................................................................ 83
Serial Timer Control Register (STCR) ................................................................ 84
Mode 1 ................................................................................................................. 86
Mode 2 ................................................................................................................. 86
Mode 3 ................................................................................................................. 86
Exception Handling Types and Priority............................................................... 91
Exception Handling Operation............................................................................. 92
Exception Sources and Vector Table ................................................................... 92
Overview.............................................................................................................. 94
Reset Sequence .................................................................................................... 94
Interrupts after Reset............................................................................................ 96
......................................................................................... 91
.................................................................................. 79

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