h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 652

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 18B Host Interface LPC Interface (LPC)
table. For information on STR3 selection, see section 18B.2.4, LPC Channel 3 Address Register
(LADR3). In an LPC I/O read cycle, the data in the selected register is transferred to the host
processor.
The STR registers are initialized to H'00 by a reset and in standby mode.
Bits 15 to 4
0000 0000 0110
0000 0000 0110
STR1, STR2 Bits 7 to 4 and 2—Defined by User (DBU17 to DBU14, DBU12; DBU27 to
DBU24, DBU22)
STR3 Bit 2— Defined by User (DBU32)
The user can use these bits as necessary.
STR1 to STR3 Bit 3—Command/Data (C/D D D D 1 to C/D D D D 3): When the host processor writes to an
IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data
or a command.
Bit 3
C/D D D D
0
1
STR1 to STR3 Bit 1—Input Buffer Full (IBF1 to IBF3A): Set to 1 when the host processor
writes to IDR. This bit is an internal interrupt source to the slave processor. IBF is cleared to 0
when the slave processor reads IDR.
The IBF1 flag setting and clearing conditions are diffrent when the fast A20 gate is used. For
details see table 18B.4.
Bit 1
IBF
0
1
Rev. 3.00 Jan 18, 2006 page 624 of 1044
REJ09B0280-0300
Description
Contents of data register (IDR) are data
Contents of data register (IDR) are a command
Description
[Clearing condition]
When the slave processor reads IDR
[Setting condition]
When the host processor writes to IDR using I/O write cycle
I/O Address
Bit 3
0
0
Bit 2
1
1
0
1
Bit 1
Bit 0
0
0
Transfer
Cycle
I/O read
I/O read
Host Register Selection
STR1 read
STR2 read
(Initial value)
(Initial value)