LTC1404 LINER [Linear Technology], LTC1404 Datasheet - Page 16

• Manufacturer Part Number: LTC1404
• Description: Complete SO-8, 12-Bit, 600ksps ADC with Shutdown
• Manufacturer: LINER [Linear Technology]

LTC1404
APPLICATIONS
inputs must be within 500mV of the supply rails). In Sleep
mode, power consumption is reduced to a minimum by
cutting off power to all internal circuitry including the
reference. Figure 12 illustrates power-down modes for the
LTC1404. The chip enters Nap mode by keeping the CLK
signal low and pulsing the CONV signal twice. For Sleep
mode operation, the CONV signal should be pulsed four
times while CLK is kept low. Nap and Sleep modes are
activated on the falling edge of the CONV pulse.
The LTC1404 returns to active mode easily. The rising
edge of CLK wakes up the LTC1404. From Nap mode,
wake-up occurs within 350ns. During the transition from
Sleep mode to active mode, the V
is a function of its loading conditions. With a 10 F bypass
capacitor, the wake-up time from Sleep mode is typically
2.5ms. A REFRDY signal is activated once the reference
has settled and is ready for an A/D conversion. This
REFRDY bit is sent to the D
by the 12-bit data word (refer to Figure 13). To save power
during wake-up from Sleep mode, the chip is designed to
enter Nap mode automatically until the reference is ready.
Once REFRDY goes high, the comparator powers up
immediately and is ready for a conversion. During the Nap
interval, any attempt to perform an analog-to-digital con-
16
REFRDY
SLEEP
CONV
D
V
CLK
NAP
OUT
REF
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS.
REFRDY APPEARS AS THE FIRST BIT IN THE D
U
t
1
INFORMATION
U
OUT
Hi-Z
pin as the first bit followed
REF
W
voltage ramp-up time
Figure 12. Nap Mode and Sleep Mode Waveforms
OUT
U
WORD
Hi-Z
t
1
Hi-Z
version will result in an all-zero output code, including the
REFRDY bit. If no conversion is attempted, the D
remains in a high impedance state. If the ADC wakes from
Sleep mode, this can be determined by monitoring the
state of the REFRDY bit at the D
DIGITAL INTERFACE
The digital interface requires only three digital lines. CLK
and CONV are both inputs, and the D
the conversion result in serial form.
Figure 13 shows the digital timing diagram of the LTC1404
during the A/D conversion. The CONV rising edge starts
the conversion. Once initiated, it can not be restarted until
the conversion is completed. If the time from CONV signal
to CLK rising edge is less than t
delayed by one clock cycle.
The digital output data is updated on the rising edge of the
CLK line. The digital output data consists of a REFRDY bit
followed by a valid 12-bit data word. D
captured by the receiving system on the rising CLK edge.
Data remains valid for a minimum time of t
rising CLK edge to allow capture to occur.
REFRDY BIT +12-BIT
REFRDY = 0
DATA WORD
ALL ZERO
Hi-Z
2,
OUT
the digital output will be
pin.
OUT
1
OUT
11
DATA WORD
REFRDY BIT
REFRDY = 1
+12-BIT
output provides
10
data should be
10
1
1404 F12
after the
0
OUT
pin