LTC1404 LINER [Linear Technology], LTC1404 Datasheet - Page 19

• Manufacturer Part Number: LTC1404
• Description: Complete SO-8, 12-Bit, 600ksps ADC with Shutdown
• Manufacturer: LINER [Linear Technology]

*Initialization*
;- - Initialized data memory to zero
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
;- - Set up the ISR vector
rint :
xint :
trnt :
txnt :
;- - Setup the reset vector
START:
*TMS320C50 Initialization*
*Configure Serial Port*
TYPICAL APPLICATIONS
THIS PROGRAM DEMONSTRATES THE LTC1404 INTERFACE TO THE
.mmregs
.ps 0A00h
.entry
SETC INTM
LDP
OPL
LACC #0
SAMM CWSR
SAMM PDWSR
SPLK #0028h, TSPC ; Set TDM Serial Port
SPLK #00E8h, TSPC ; Take Serial Port out of reset
SPLK #0FFFFh, IFR
TMS320C50. FRAME SYNC PULSE IS GENERATED FROM TFSX.
.ds
.word
.word
.word
.word
.word
.word
.ps
B
B
B
B
#0
#0834h, PMST ; Set up the PMST status and control register
DATA SHIFT CLOCK IS EXTERNALLY GENERATED.
0
0
0
0
0
0
TREC
TTRANX
0F00h
080Ah
RECEIVE
TRANSMIT
; Temporarily disable all interrupts
; Set data page pointer to zero
; Set software wait state to 0
;
; TDM = 0 Stand Alone mode
; DLB=0 Not loop back
; FO=0 16 Bits
; FSM=1 Burst Mode
; MCM=0 CLKR is generated externally
; TXM=1 FSX as output pin
; Put serial port into reset
; (XRST=RRST=0)
; (XRST=RRST=1)
; Clear all the pending interrupts
; Defines global symbolic names
; Initialize data to zero
; Begin sample data location
; .
; Location of data
; .
; .
; End sample data location
; Serial ports interrupts
; 0A;
; 0C;
; 0E;
; 10;
U
TMS320C50 Code for Circuit
*Start Serial Communication*
WAIT:
; - - - - - - - end of main program - - - - - - - - - - ;
*Receiver Interrupt Service Routine*
TREC:
*After Obtained the Data from LTC1404, Program Jump to END_TRCV*
END_TRCV:
SUCCESS:
*Fill the Unused Interrupt with RETE, to avoid program get “lost”*
TTRANX:
RECEIVE:
TRANSMIT:
INT2:
SACL TDXR
SPLK #040h, IMR
CLRC INTM
CLRC SXM
MAR *, AR7
LAR
SACL TDXR
B
LAMM TRCV
SFR
SFR
AND #1FFFh, 0
SACL *+, 0
LACC AR7
SUB #0F05h,0
BCND END_TRCV, GEQ ; If the end sample address has exceeded jump
SPLK #040h, IMR
RETE
SPLK #002h, IMR
CLRC INTM
B
RETE
RETE
RETE
B halt
AR7, #0F00h
NOP
NOP
NOP
WAIT
SUCCESS
; Generate frame sync pulse
; Turn on TRNT receiver interrupt
; Enable interrupt
; For Unipolar input, set for right shift
; with no sign extension
; Load the auxiliary register pointer with seven
; Load the auxiliary register seven with #0F00h
; as the begin address for data storage
; Wait for a receive interrupt
;
;
; !! Regenerate the frame sync pulse
;
; Load the data received from LTC1404
; Shift right two times
;
; ANDed with #1FFFh
; For converting the data to right
; justified format
;
; Write to data memory pointed by AR7 and
; increase the memory address by one
;
; Compare to end sample address #0F05h
;
; Else Re-enable the TRNT receive interrupt
; Return to main program and enable interrupt
; Enable INT2 for program to halt
; Halts the running CPU
to END_TRCV
LTC1404
19