LTC1647 LINER [Linear Technology], LTC1647 Datasheet - Page 16

• Manufacturer Part Number: LTC1647
• Description: Hot Swap Controller
• Manufacturer: LINER [Linear Technology]

OPERATION
a start-up check to make sure the supply voltage is above
its 2.3V UVLO threshold (see Time Point 1). If the input
supply voltage is valid, the gate of the external pass tran-
sistor is pulled to ground by the internal 200μA current
source connected at the GATE pin. The TIMER pin is held
low by an internal N-channel pull-down transistor (see
M6, LTC4211 Block Diagram) and the FILTER pin voltage
is pulled to ground by an internal 10μA current source.
Once V
LTC4211 checks to make sure that GATE is OFF (V
0.2V) at Time Point 2. An internal timing circuit is enabled
and the TIMER pin voltage ramps up at the rate described by
Equation 1. At Time Point 3 (the timing period programmed
by C
Next, the TIMER pin voltage ramps down to Time Point 4
where the LTC4211 performs two checks: (1) FILTER pin
voltage is low (V
age is high (V
the LTC4211 begins a second timing (soft-start) cycle.
Second Timing (Soft-Start) Cycle
At the beginning of the second timing cycle (Time Point 5),
the LTC4211’s FAST COMP is armed and an internal 10μA
current source working with an internal charge pump
provides the gate drive to the external pass transistor. The
LTC4211 automatically limits the inrush current in one of
two ways: by controlling the GATE pin voltage slew rate
or by actively limiting the inrush current. If GATE voltage
slew rate control is preferred, an external capacitor C
can be used from GATE to ground, as shown in Figure 6.
LTC4211
16
V
5V
**
IN
*
VALUES ≤150nF SUGGESTED
ADDITIONAL DETAILS OMITTED
FOR CLARITY
TIMER
Figure 6. Using an External Capacitor at GATE for
GATE Voltage Slew Rate Control
CC
), the TIMER pin voltage equals V
V
and ON (the ON pin is >1.316) are valid, the
CC
0.007Ω
R
SENSE
FAULT
SENSE
LTC4211**
FILTER
> 1.286V). If both conditions are met,
< 1.156V) and (2) FAULT pin volt-
Si4410DY
GATE
M1
FB
C
dV
GATE
V
GATE
GATE
dt
*
SLEW RATE CONTROL
=
(
R1
36k
R2
15k
4211 F06
C
10μA
GATE
TMR
+
)
C
(1.236V).
LOAD
GATE
V
5V
5A
OUT
GATE
<
An expression for the GATE voltage slew rate is given by
Equation 3:
Adding C
pense of slower system turn-on and turn-off time. Should
this technique be used, values for C
are recommended.
The inrush current being delivered to the load while
the GATE is ramping is dependent on C
Equation 4 gives an expression for the inrush current
during the second timing cycle:
For example, if C
inrush current charging C
At Time Point 6, the output voltage trips COMP2’s thresh-
old, signaling an output voltage “power good” condition.
At Time Point 7, RESET is asserted high, SLOW COMP is
armed and the LTC4211 enters a fault monitor mode. The
TIMER voltage then ramps down to Time Point 8.
Power-Off Cycle
As shown at Time Point 9, an external hard reset is initiated
by pulling the ON pin low (V
voltage is ramped to ground by the internal 200μA cur-
rent source, discharging C
transistor. As C
COMP2’s threshold, signaling a “power bad” condition at
Time Point 10. At this point, RESET is asserted low.
I
I
V
INRUSH
INRUSH
GATE
GATE
Slew Rate,
= 10µA •
=
dV
slows the GATE voltage slew rate at the ex-
LOAD
GATE
dt
GATE
discharges, the output voltage crosses
0.0033µF
dV
2000µF
• C
= 3300pF and C
GATE
dt
LOAD
LOAD
GATE
ON
=
= 10µA •
is:
= 6.06A
< 1.236V). The GATE pin
C
and turning off the pass
10µA
GATE
GATE
LOAD
C
C
LOAD
less than 150nF
LOAD
GATE
= 2000μF, the
and C
GATE
4211fb
(3)
(4)
(5)
.