LT1460-2.5 LINER [Linear Technology], LT1460-2.5 Datasheet - Page 15

• Manufacturer Part Number: LT1460-2.5
• Description: Serial 12-Bit/14-Bit, 2.8Msps
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
One or more rising edges at SCK wake up the LTC1403-1/
LTC1403A-1 for service very quickly, and CONV can start
an accurate conversion within a clock cycle. Four rising
edges at CONV, without any intervening rising edges at
SCK, put the LTC1403-1/LTC1403A-1 in Sleep mode and
the power drain drops from 16mW to 10µW. One or more
rising edges at SCK wake up the LTC1403-1/LTC1403A-1
for operation. The internal reference (V
slew and settle with a 10µF load. Note that, using sleep
mode more frequently than every 2ms, compromises the
settled accuracy of the internal reference. Note that, for
slower conversion rates, the Nap and Sleep modes can be
used for substantial reductions in power consumption.
DIGITAL INTERFACE
The LTC1403-1/LTC1403A-1 has a 3-wire SPI (Serial Pro-
tocol Interface) interface. The SCK and CONV inputs and
SDO output implement this interface. The SCK and CONV
inputs accept swings from 3V logic and are TTL compat-
ible, if the logic swing does not exceed V
description of the three serial port signals follows:
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but
subsequent rising edges at CONV are ignored by the
LTC1403-1/LTC1403A-1 until the following 16 SCK rising
edges have occurred. It is necessary to have a minimum
of 16 rising edges of the clock input SCK between ris-
ing edges of CONV. But to obtain maximum conversion
speed, it is necessary to allow two more clock periods
between conversions to allow 39ns of acquisition time
for the internal ADC sample-and-hold circuit. With 16
clock periods per conversion, the maximum conversion
rate is limited to 2.8Msps to allow 39ns for acquisition
time. In either case, the output data stream comes out
within the first 16 clock periods to ensure compatibility
with processor serial ports. The duty cycle of CONV can
be arbitrarily chosen to be used as a frame sync signal for
the processor serial port. A simple approach to generate
CONV is to create a pulse that is one SCK wide to drive the
LTC1403-1/LTC1403A-1 and then buffer this signal with
the appropriate number of inverters to ensure the correct
REF
) takes 2ms to
DD
. A detailed
delay driving the frame sync input of the processor serial
port. It is good practice to drive the LTC1403-1/LTC1403A-1
CONV input first to avoid digital noise interference during
the sample-to-hold transition triggered by CONV at the
start of conversion. It is also good practice to keep the
width of the low portion of the CONV signal greater than
15ns to avoid introducing glitches in the front end of the
ADC just before the sample-and-hold goes into hold mode
at the rising edge of CONV.
Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sinewaves
above 100kHz are sampled, the CONV signal must have
as little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement easily. The challenge is to generate a CONV
signal from this crystal clock without jitter corruption from
other digital circuits in the system. A clock divider and
any gates in the signal path from the crystal clock to the
CONV input should not share the same integrated circuit
with other parts of the system. As shown in the interface
circuit examples, the SCK and CONV inputs should be
driven first, with digital buffers used to drive the serial port
interface. Also note that the master clock in the DSP may
already be corrupted with jitter, even if it comes directly
from the DSP crystal. Another problem with high speed
processor clocks is that they often use a low cost, low
speed crystal (i.e., 10MHz) to generate a fast, but jittery,
phase-locked-loop system clock (i.e., 40MHz). The jitter
in these PLL-generated high speed clocks can be several
nanoseconds. Note that if you choose to use the frame
sync signal generated by the DSP port, this signal will
have the same jitter of the DSP’s master clock.
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK starts clocking
out the 12/14 data bits with the MSB sent first. A simple
approach is to generate SCK to drive the LTC1403-1/
LTC1403A-1 first and then buffer this signal with the
appropriate number of inverters to drive the serial clock
input of the processor serial port. Use the falling edge of
LTC1403-1/LTC1403A-1
15
14031fc