LT1460-2.5 LINER [Linear Technology], LT1460-2.5 Datasheet - Page 16

• Manufacturer Part Number: LT1460-2.5
• Description: Serial 12-Bit/14-Bit, 2.8Msps
• Manufacturer: LINER [Linear Technology]

LTC1403-1/LTC1403A-1
APPLICATIONS INFORMATION
the clock to latch data from the Serial Data Output (SDO)
into your processor serial port. The 14-bit Serial Data
will be received right justified, in a 16-bit word with 16 or
more clocks per frame sync. It is good practice to drive
the LTC1403-1/LTC1403A-1 SCK input first to avoid digi-
tal noise interference during the internal bit comparison
decision by the internal high speed comparator. Unlike the
CONV input, the SCK input is not sensitive to jitter because
the input signal is already sampled and held constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends
out 12/14 bits in 2’s complement format in the output data
stream beginning at the third rising edge of SCK after the
rising edge of CONV. SDO is always in high impedance
mode when it is not sending out data bits. Please note
the delay specification from SCK to a valid SDO. SDO is
always guaranteed to be valid by the next rising edge of
SCK. The 16-bit output data stream is compatible with the
16-bit or 32-bit serial port of most processors.
16
LTC1403A-1
LTC1403-1/
CONV
GND
SDO
V
SCK
DD
7
10
9
8
6
3V
Figure 8. DSP Serial Interface to TMS320C54x
CONV
CLK
0V TO 3V LOGIC SWING
INTERFACELINK
3-WIRE SERIAL
HARDWARE INTERFACE TO TMS320C54x
The LTC1403-1/LTC1403A-1 is a serial output ADC whose
interface has been designed for high speed buffered serial
ports in fast digital signal processors (DSPs). Figure 8
shows an example of this interface using a TMS320C54x.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial
data can be collected in two alternating 1kB segments,
in real time, at the full 2.8Msps conversion rate of the
LTC1403-1/LTC1403A-1. The DSP assembly code sets
frame sync mode at the BFSR pin to accept an external
positive going pulse and the serial clock at the BCLKR pin
to accept an external positive edge clock. Buffers near
the LTC1403-1/LTC1403A-1 may be added to drive long
tracks to the DSP to prevent corruption of the signal to
LTC1403-1/LTC1403A-1. This configuration is adequate to
traverse a typical system board, but source resistors at the
buffer outputs and termination resistors at the DSP, may
be needed to match the characteristic impedance of very
long transmission lines. If you need to terminate the SDO
transmission line, buffer it first with one or two 74ACTxx
gates. The TTL threshold inputs of the DSP port respond
properly to the 3V swing from the SDO pin.
B13
B12
5V
TMS320C54x
V
BFSR
BCLKR
BDR
CC
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