LTC1864 LINER [Linear Technology], LTC1864 Datasheet - Page 9

• Manufacturer Part Number: LTC1864
• Description: ?Power, 16-Bit, 250ksps 1- and 2-Channel ADCs in MSOP
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC1864 OPERATION
Operating Sequence
The LTC1864 conversion cycle begins with the rising edge
of CONV. After a period equal to t
finished. If CONV is left high after this time, the LTC1864
goes into sleep mode drawing only leakage current. On the
falling edge of CONV, the LTC1864 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefinitely. See Figure 1.
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CONV
SDO
SCK
•
•
•
Figure 2. LTC1864 Transfer Curve
U
t
CONV
U
*V
CONV
W
IN
Hi-Z
= IN
, the conversion is
+
Figure 1. LTC1864 Operating Sequence
– IN
–
SLEEP MODE
U
1864 F02
Analog Inputs
The LTC1864 has a unipolar differential analog input. The
converter will measure the voltage between the “IN
“IN
equals zero. Full scale occurs when IN
V
“IN
mode noise on the inputs is rejected by the ADC. If “IN
is grounded and V
will result on “IN
Reference Input
The voltage on the reference input of the LTC1864 defines
the full-scale range of the A/D converter. The LTC1864 can
operate with reference voltages from V
REF
V
IN
–
–
*
B15 B14
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
” inputs. A zero code will occur when IN
” inputs are sampled at the same time, so common
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1
minus 1LSB. See Figure 2. Both the “IN
V
2
IN
B13
= 0V TO V
3
Figure 3. LTC1864 with Rail-to-Rail Input Span
B12
4
B11
5
CC
+
B10
REF
” as shown in Figure 3.
6
1
2
3
4
B9
V
IN
IN
GND
is tied to V
7
REF
t
+
–
SMPL
B8
LTC1864
LTC1864/LTC1865
8
B7
9
CONV
SDO
SCK
V
B6
1µF
10
CC
B5
CC
11
1864 F03
8
7
6
5
, a rail-to-rail input span
B4
12
B3
13
V
+
CC
CC
minus IN
B2
14
B1
to 1V.
15
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
1854 F01
B0*
+
16
minus IN
sn18645 18645fs
Hi-Z
–
+
equals
+
” and
” and
9
–
–
”