P2010 FREESCALE [Freescale Semiconductor, Inc], P2010 Datasheet - Page 2

• Manufacturer Part Number: P2010
• Description: single- and dual-core communications processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Target Applications
The P2010 and P2020 processors serve
in a wide range of applications, especially
those that have tight thermal constraints.
With an available junction temperature
range of -40°C to +125°C, the devices
can be used in power-sensitive defense,
aerospace and industrial applications, and
less-protected outdoor environments. They
enable various combinations of data plane
and control plane workloads in networking
and telecom applications that require higher
performance but want to avoid the complexity
of partitioning the application across many
cores. The devices’ primary target applications
are networking and telecom linecards. The P2
devices, with their low power budget and high
single-threaded performance, are uniquely
well-suited for control plane applications.
Control plane applications tend to be more
sequential in nature and thus lose scaling
efficiency with increasing number of threads
or cores. The P2 series, with its low power,
efficient dual-issue out-of-order e500 core,
Power Architecture technology, and high
1.2 GHz frequency, offers a level of single-
threaded performance that is a perfect fit for
control plane applications.
The networking linecard requires an optimal
combination of good performance to manage
a large amount of control plane traffic
balanced against low power and cost. With
convenient I/O, flexible core configurations
and an on-board security block, the P2010
and P2020 processors are well-suited for this
application, which involves controlling
ASICs, managing exceptions and routing
table maintenance.
QorIQ™ Platform
P1
P1
P2
P2
Freescale, QorIQ, CoreNet and the Freescale logo are trademarks or registered trademarks of Freescale Semiconductor, Inc.
in the U.S. and other countries. All other product or service names are the property of their respective owners.
The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are
trademarks and service marks licensed by Power.org. © Freescale Semiconductor, Inc. 2009.
Document Number: QP20XXFS
REV 3
Device
P1011
P1020
P2010
P2020
Cores
1
2
1
2
Top Core Frequency
1200 MHz
1200 MHz
800 MHz
800 MHz
The P2010 and P2020 processors are also
well-suited for Long Term Evolution (LTE)
and WiMAX channel card applications.
With dual-core performance in single-core
power budgets, the P2 series facilitates the
“flattening” of the wireless network hierarchy.
The dual Serial RapidIO interfaces allow
direct connection to the DSPs (such as
Freescale’s MSC8156 DSP) that implement
Layer 1 processing as well as redundant
backplane connections.
Technical Specifications
• Dual (P2020) or single (P2010)
• 512 KB L2 cache with ECC. Also
• Three 10/100/1000 Mbps enhanced three-
high-performance Power Architecture
e500 cores
configurable as SRAM and stashing
memory.
speed Ethernet controllers (eTSECs)
36-bit physical addressing
Double-precision floating-point support
32 KB L1 instruction cache and 32 KB L1
data cache for each core
800 MHz to 1.2 GHz clock frequency
TCP/IP acceleration and classification
capabilities
IEEE 1588 support
Lossless flow control
R/G/MII, R/TBI, SGMII
FIFO interfaces
L2 Size
256 KB
256 KB
512 KB
512 KB
DDR 2/3 Support
32-bit with ECC
32-bit with ECC
64-bit with ECC
64-bit with ECC
Learn More:
GE Ports
3
3
3
3
SerDes
• High-speed interfaces supporting various
• High-Speed USB controller (USB 2.0)
• Enhanced secure digital host controller
• Serial peripheral interface
• Integrated security engine (SEC 3.1)
• 64-bit DDR2/DDR3 SDRAM memory
• Programmable interrupt controller (PIC)
• Two four-channel DMA controllers
• Two I
• Enhanced local bus controller (eLBC)
• 16 general-purpose I/O signals
• Package: 689-pin wirebond power-BGA
For current information about Freescale
products and documentation, please visit
www.freescale.com/QorIQ.
4
4
4
4
multiplexing options
(SD/MMC)
(optional)
controller with ECC support
compliant with OpenPIC standard
(TEPBGA2)
Four SerDes to 3.125 GHz multiplexed
across controllers
Three PCI Express interfaces
Two Serial RapidIO interfaces
Two SGMII interfaces
Host and device support
Enhanced host controller interface (EHCI)
ULPI interface to PHY
Crypto algorithm support includes 3DES,
AES, RSA/ECC, MD5/SHA, ARC4, Kasumi,
Snow 3G and FIPS deterministic RNG
Single pass encryption/message
authentication for common security
protocols (IPsec, SSL, SRTP, WiMAX)
XOR acceleration
2
C controllers, DUART, timers
PCI Express
2
2
3
3
®
Serial RapidIO
N/A
N/A
2
2
®
TDM
Yes
Yes
N/A
N/A