LTC2272CUJ LINER [Linear Technology], LTC2272CUJ Datasheet
LTC2272CUJ
Related parts for LTC2272CUJ
LTC2272CUJ Summary of contents
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FEATURES n High Speed Serial Interface (JESD204) n Sample Rate: 80Msps/65Msps n 77.7dBFS Noise Floor n 100dB SFDR n SFDR >90dB at 140MHz (1.5V P-P n PGA Front End (2.25V or 1.5V P-P n 700MHz Full Power Bandwidth S/H n ...
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... LTC2273CUJ LTC2273CUJ#TR LTC2273IUJ LTC2273IUJ#TR LTC2272CUJ LTC2272CUJ#TR LTC2272IUJ LTC2272IUJ#TR Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi label on the shipping container. For more information on lead free part marking, go to: For more information on tape and reel specifi cations, go to: CONVERTER CHARACTERISTICS temperature range, otherwise specifi ...
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ANALOG INPUT l The denotes denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are 25°C. (Note 4) A SYMBOL PARAMETER V Analog Input Range ( Analog Input ...
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LTC2273/LTC2272 DYNAMIC ACCURACY otherwise specifi cations are 25° SYMBOL PARAMETER CONDITIONS SFDR Spurious Free Dynamic 5MHz Input (2.25V Range, PGA = 0) th Range 4 Harmonic or 5MHz Input (1.5V Range, PGA = 1) Higher ...
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COMMON MODE BIAS CHARACTERISTICS the full operating temperature range, otherwise specifi cations are at T PARAMETER CONDITIONS V Output Voltage OUT V Output Tempco OUT V Line Regulation 3.135V ≤ ...
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LTC2273/LTC2272 POWER REQUIREMENTS range, otherwise specifi cations are SYMBOL PARAMETER CONDITIONS V Analog Supply Voltage DD P Shutdown Power SHDN = V SHDN OV Output Supply Voltage CMLOUT Directly-Coupled, 50Ω CMLOUT Directly-Coupled, 100Ω Diff. ...
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TIMING DIAGRAMS ANALOG INPUT + ENC INTERNAL N – 6 PARALLEL DATA INTERNAL N – 9 8B/10B DATA t BIT + – CMLOUT /CMLOUT N – CONV N – 1 ANALOG INPUT ENC t CS(MIN) ...
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LTC2273/LTC2272 TYPICAL PERFORMANCE CHARACTERISTICS unless otherwise noted. LTC2273: Integral Non-Linearity (INL) vs Output Code 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0 16384 32768 49152 65536 OUTPUT CODE 22732 G01 LTC2273: 128k Point FFT 5.1MHz, –1dBFS, ...
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TYPICAL PERFORMANCE CHARACTERISTICS unless otherwise noted. LTC2273: 64k Point 2-Tone FFT 14.01MHz and 15.8MHz, IN –15dBFS, PGA = 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY ...
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LTC2273/LTC2272 TYPICAL PERFORMANCE CHARACTERISTICS unless otherwise noted. LTC2273: 64k Point FFT 250.2MHz, –1dBFS, PGA = –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) 22732 ...
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TYPICAL PERFORMANCE CHARACTERISTICS unless otherwise noted. LTC2272: Integral Non-Linearity (INL) vs Output Code 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0 16384 32768 49152 65536 OUTPUT CODE 22732 G26 LTC2272: 128k Point FFT 5.1MHz, –1dBFS, PGA ...
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LTC2273/LTC2272 TYPICAL PERFORMANCE CHARACTERISTICS unless otherwise noted. LTC2272: 64k Point FFT 14.01MHz and 15.8MHz, IN –15dBFS, PGA = 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY ...
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TYPICAL PERFORMANCE CHARACTERISTICS unless otherwise noted. LTC2272: 64k Point FFT 250.2MHz, –1dBFS, PGA = –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) 22732 G44 ...
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LTC2273/LTC2272 TYPICAL PERFORMANCE CHARACTERISTICS otherwise noted. CMLOUT Dual-Dirac BER Bathtub Curve, 400Mbps 1.0E+00 1.0E–02 1.0E–04 1.0E–06 1.0E–08 1.0E – 10 1.0E–12 1.0E–14 0 0.2 0.4 UNIT INTERVAL (UI) CMLOUT Dual-Dirac BER Bathtub Curve, 1.6Gbps 1.0E+00 1.0E–02 1.0E–04 1.0E–06 1.0E–08 1.0E ...
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PIN FUNCTIONS V (Pins Analog 3.3V Supply. Bypass to DD GND with 0.1μF ceramic chip capacitors. GND (Pins 11, 14, 21, 26, 27, 30, 37, 40, 41): ADC Power Ground. + ...
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LTC2273/LTC2272 PIN FUNCTIONS FAM (Pin 31): Frame Alignment Monitor Enable. A high level enables the substitution of predetermined data at the end of the frame with a K28.7 symbol for frame alignment monitoring. PAT0 (Pin 32): Pattern Select Bit0. Use ...
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BLOCK DIAGRAM + + A S/H IN FIRST SECOND AND PGA STAGE STAGE – – DITHER SIGNAL GENERATOR REFERENCE CONTROL ADC SENSE REFERENCE 0. CLOCK DRIVER 2.5V WITH DUTY CYCLE REFERENCE CONTROL + ...
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LTC2273/LTC2272 DEFINITIONS DYNAMIC PERFORMANCE TERMS Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. ...
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DEFINITIONS the standard defi nes an additional set of 12 special code- groups for non-data characters such as commas. Special code-group names begin with K instead complete 8B/10B description is found in Clause 36.2 of IEEE Std ...
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LTC2273/LTC2272 DEFINITIONS a D16.2 will be transmitted after the comma, otherwise a D5.6 will be transmitted. The result is that the ending disparity of an idle ordered set will always be negative. Initial Frame Synchronization The process of communicating frame ...
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APPLICATIONS INFORMATION CONVERTER OPERATION The core of the LTC2273/LTC2272 are CMOS pipelined multi-step converters with a front-end PGA. As shown in Figure 1, the converter has fi ve pipelined ADC stages. A sampled analog input will result in a digitized ...
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LTC2273/LTC2272 APPLICATIONS INFORMATION SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2273/ LTC2272 CMOS differential sample and hold. The differ- ential analog inputs are sampled directly onto sampling capacitors (C ) through NMOS ...
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APPLICATIONS INFORMATION INPUT DRIVE CIRCUITS Input Filtering A fi rst order RC lowpass fi lter at the input of the ADC can serve two functions: limit the noise from input cir- cuitry and provide isolation from ADC S/H switching. The ...
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LTC2273/LTC2272 APPLICATIONS INFORMATION Direct Coupled Circuits Figure 5 demonstrates the use of a differential amplifi convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input ...
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APPLICATIONS INFORMATION 1.25V 2.2μF 6 SENSE 2, 3 3.3V LTC6652-2.5 1μF 2.2μ Figure 7. A 2.25V Range ADC with an External 2.5V Reference 0.1μF T1 50Ω 100Ω 8.2pF 50Ω 0.1μF 0.1μ MA/COM ETC1-1-13 RESISTORS ...
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LTC2273/LTC2272 APPLICATIONS INFORMATION Driving the Encode Inputs The noise performance of the LTC2273/LTC2272 can depend on the encode signal quality as much as for the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity ...
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APPLICATIONS INFORMATION LTC2273/LTC2272 + AIN ANALOG S/H INPUT AMP – AIN CLOCK/DUTY CYCLE CONTROL + – ENC ENC Figure 11. Functional Equivalent Block Diagram of Internal Dither Circuit SERIALIZED DATA FRAME Prior to serialization, the ADC data is encoded into ...
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LTC2273/LTC2272 APPLICATIONS INFORMATION ANALOG INPUT + ENC INTERNAL N – 6 PARALLEL DATA INTERNAL N – 9 8B/10B DATA t BIT SERIAL DATA OUT N – 10 Figure 13. Timing Relationship of Analog Sample to Serial Data Out Initial Frame ...
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APPLICATIONS INFORMATION t CONV N N – 1 ANALOG INPUT ENC t CS(MIN) + SYNC t CS(MAX) SERIAL DATA OUT N – 10 Figure 14a. SYNC t CONV N – 1 ANALOG INPUT ENC ...
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LTC2273/LTC2272 APPLICATIONS INFORMATION NO DATA TRANSMISSION FLOW (SEE FIGURE 18) AS CODE GROUP 1 AS CODE GROUP 2 Scrambling To avoid spectral interference from the serial data output, an optional data scrambler is added between the ADC data and the ...
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APPLICATIONS INFORMATION SECOND OCTET FROM ADC D8 D9 D10 D11 FIRST OCTET D12 D13 D13 D15 MSB Figure 16. LTC2273/LTC2272 16-Bit LTC2273/LTC2272 SAMPLE_CLK SS0 SS1 ...
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LTC2273/LTC2272 APPLICATIONS INFORMATION FRAME_CLK SECOND SCRAMBLED OCTET FROM 8B/10B DECODER FIRST SCRAMBLED OCTET Figure 17. Required 16-Bit SS0 SS1 SS2 SS3 ...
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APPLICATIONS INFORMATION Frame Alignment Monitoring After the initial synchronization has been established, it may be desirable to periodically verify that frame alignment is being maintained. The receiver may issue a synchroniza- tion request at any time, but data will be ...
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LTC2273/LTC2272 APPLICATIONS INFORMATION START SCRAMBLE ADC DATA IF SCRAM IS ENABLED GENERATE 8B/10B CODE-GROUPS 1 AND FAM ENABLED? TRANSMIT CODE GROUP 1 TRANSMIT CODE GROUP 2 NO TRANSMIT CODE GROUP 2 22732 F18 PLL Operation The PLL ...
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APPLICATIONS INFORMATION High Speed CML Outputs The CML outputs must be terminated for proper opera- tion. The OV supply voltage and the termination voltage DD determine the common mode output level of the CML outputs. For proper operation of the ...
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LTC2273/LTC2272 APPLICATIONS INFORMATION SERIAL CML DRIVER 50Ω + DATA – DATA GND Figure 19a. CML Termination, Directly-Coupled Mode (Preferred) SERIAL CML DRIVER 50Ω + DATA – DATA GND Figure 19b. CML Termination, Directly-Coupled Differential Mode 36 1.2V TO 3.3V OV ...
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APPLICATIONS INFORMATION SERIAL CML DRIVER 50Ω + DATA – DATA 16mA GND 1.4V TO 3.3V VTERM OV DD 50Ω 50Ω 0.01μF TRANSMISSION LINE + CMLOUT 0.01μF – CMLOUT 50Ω TRANSMISSION LINE Figure 19c. CML Termination, AC-Coupled Mode LTC2273/LTC2272 SERIAL CML ...
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LTC2273/LTC2272 TYPICAL APPLICATIONS 38 Silkscreen Top Top Side 22732f ...
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TYPICAL APPLICATIONS LTC2273/LTC2272 Inner Layer 2 Inner Layer 3 22732f 39 ...
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LTC2273/LTC2272 TYPICAL APPLICATIONS 40 Inner Layer 4 Inner Layer 5 22732f ...
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TYPICAL APPLICATIONS LTC2273/LTC2272 Bottom Side Silkscreen Bottom 22732f 41 ...
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LTC2273/LTC2272 TYPICAL APPLICATIONS DD V SCRAM FAM P1 PDSER P2 PDADC P3 MSBINV P4 NC PGA P5 NC PAT1 P6 NC PAT0 DITH ISMODE P1 PLL0 P2 PLL1 P3 RX_ER ...
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PACKAGE DESCRIPTION 4.42 0.05 4.42 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 0.10 (4 SIDES) PIN 1 TOP MARK (SEE NOTE 6) NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE ...
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LTC2273/LTC2272 RELATED PARTS PART NUMBER DESCRIPTION LTC1993-2 High Speed Differential Op Amp LTC1994 Low Noise, Low Distortion Fully Differential Input/ Output Amplifi er/Driver LTC2215 16-Bit, 65Msps, Low Noise ADC LTC2216 16-Bit, 80Msps, Low Noise ADC LTC2217 16-Bit, 105Msps, Low Noise ...