LTC2272CUJ LINER [Linear Technology], LTC2272CUJ Datasheet - Page 22

• Manufacturer Part Number: LTC2272CUJ
• Description: 16-Bit, 80Msps/65Msps Serial Output ADC
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2273/
LTC2272 CMOS differential sample and hold. The differ-
ential analog inputs are sampled directly onto sampling
capacitors (C
capacitors shown attached to each input (C
the summation of all other capacitance associated with
each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track, the differential
input voltage. On the rising edge of ENC, the sampled
input voltage is held on the sampling capacitors. During
the hold phase when ENC is high, the sampling capacitors
are disconnected from the input and the held voltage is
passed to the ADC core for processing. As ENC transitions
for high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such
as the change seen with input frequencies near Nyquist,
then a larger charging glitch will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential drive
to achieve specifi ed performance. Each input should swing
±0.5625V for the 2.25V range (PGA = 0) or ±0.375V for
the 1.5V range (PGA = 1), around a common mode volt-
age of 1.25V. The V
provide the common mode bias level. V
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The V
close to the ADC with 2.2μF or greater.
LTC2273/LTC2272
22
SAMPLE
CM
CM
) through NMOS transistors. The
output pin (Pin 39) is designed to
pin must be bypassed to ground
CM
PARASITIC
can be tied
) are
Input Drive Impedance
As with all high performance, high speed ADCs the
dynamic performance of the LTC2273/LTC2272 can be
infl uenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and in-
put reactance can infl uence SFDR. At the falling edge of
ENC the sample-and-hold circuit will connect the 4.9pF
sampling capacitor to the input pin and start the sampling
period. The sampling period ends when ENC rises, hold-
ing the sampled input on the sampling capacitor. Ideally,
the input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
ENC
ENC
A
A
IN
IN
ENCODE
+
+
–
–
LTC2273/LTC2272
V
1.6V
1.6V
DD
); however, this is not always possible and the
Figure 2. Equivalent Input Circuit
6k
6k
V
DD
V
R
R
DD
PARASITIC
PARASITIC
3Ω
3Ω
C
1.8pF
C
1.8pF
PARASITIC
PARASITIC
20Ω
20Ω
R
R
ON
ON
C
C
SAMPLE
SAMPLE
4.9pF
4.9pF
22732 F02
22732f